| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-riscv.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
11 #define pr_fmt(fmt) "riscv-timer: " fmt
16 #include <linux/cpu.h>
22 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <clocksource/timer-riscv.h>
89 static int riscv_timer_starting_cpu(unsigned int cpu) in riscv_timer_starting_cpu() argument
91 struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); in riscv_timer_starting_cpu()
93 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
94 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
20 from simple wfi to power gating) according to OS PM policies. The CPU states
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| /openbmc/linux/drivers/firmware/psci/ |
| H A D | psci_checker.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/cpu.h>
31 static int tos_resident_cpu = -1;
42 * "enable-method" property of each CPU in the DT, but given that there is no
43 * arch-specific way to check this, we assume that the DT is sensible.
47 int migrate_type = -1; in psci_ops_check()
48 int cpu; in psci_ops_check() local
52 return -EOPNOTSUPP; in psci_ops_check()
61 for_each_online_cpu(cpu) in psci_ops_check()
62 if (psci_tos_resident_on(cpu)) { in psci_ops_check()
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| /openbmc/linux/kernel/time/ |
| H A D | timer.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-01-28 Modified by Finn Arne Gangstad to make timers scale better.
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
11 * 1998-12-24 Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
14 * 1999-03-10 Improved NTP compatibility by Ulrich Windl
15 * 2002-05-31 Move sys_sysinfo here and make its locking sane, Robert Love
16 * 2000-10-05 Implemented scalable SMP per-CPU timer handling.
33 #include <linux/posix-timers.h>
34 #include <linux/cpu.h>
55 #include "tick-internal.h"
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| H A D | tick-broadcast.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains functions which emulate a local clock-event
6 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
7 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
8 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner
10 #include <linux/cpu.h>
20 #include "tick-internal.h"
24 * timer stops in C3 state.
39 static void tick_broadcast_clear_oneshot(int cpu);
42 static void tick_broadcast_oneshot_offline(unsigned int cpu);
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| /openbmc/linux/kernel/futex/ |
| H A D | waitwake.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 * In futex wake up scenarios where no tasks are blocked on a futex, taking
33 * CPU 0 CPU 1
39 * sys_futex(WAKE, futex);
49 * This would cause the waiter on CPU 0 to wait forever because it
57 * CPU 0 CPU 1
63 * smp_mb(); (A) <-- paired with -.
69 * | sys_futex(WAKE, futex);
72 * `--------> smp_mb(); (B)
79 * waiters--; (b) unlock(hash_bucket(futex));
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| /openbmc/linux/lib/ |
| H A D | Kconfig.kfence | 1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "KFENCE: low-overhead sampling-based memory safety error detector"
12 KFENCE is a low-overhead sampling-based detector of heap out-of-bounds
13 access, use-after-free, and invalid-free errors. KFENCE is designed
17 See <file:Documentation/dev-tools/kfence.rst> for more details.
23 environments. If your kernel targets production use, and cannot
37 setting "kfence.sample_interval" to a non-zero value enables KFENCE.
49 bool "Use a deferrable timer to trigger allocations"
51 Use a deferrable timer to trigger allocations. This avoids forcing
52 CPU wake-ups if the system is idle, at the risk of a less predictable
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| /openbmc/linux/kernel/rcu/ |
| H A D | tree_nocb.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions that provide either classic
21 return lockdep_is_held(&rdp->nocb_lock); in rcu_lockdep_is_held_nocb()
27 if (!rdp->nocb_cb_kthread || !rdp->nocb_gp_kthread) in rcu_current_is_nocb_kthread()
30 if (current == rdp->nocb_cb_kthread || current == rdp->nocb_gp_kthread) in rcu_current_is_nocb_kthread()
37 * Offload callback processing from the boot-time-specified set of CPUs
39 * created that pull the callbacks from the corresponding CPU, wait for
43 * invoke callbacks. Each GP kthread invokes its own CBs. The no-CBs CPUs
46 * in which case each kthread actively polls its CPU. (Which isn't so great
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| /openbmc/linux/arch/arm64/kvm/ |
| H A D | arm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
9 #include <linux/entry-kvm.h>
77 if (cap->flags) in kvm_vm_ioctl_enable_cap()
78 return -EINVAL; in kvm_vm_ioctl_enable_cap()
80 switch (cap->cap) { in kvm_vm_ioctl_enable_cap()
84 &kvm->arch.flags); in kvm_vm_ioctl_enable_cap()
87 mutex_lock(&kvm->lock); in kvm_vm_ioctl_enable_cap()
88 if (!system_supports_mte() || kvm->created_vcpus) { in kvm_vm_ioctl_enable_cap()
89 r = -EINVAL; in kvm_vm_ioctl_enable_cap()
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| /openbmc/qemu/hw/arm/ |
| H A D | npcm7xx.c | 21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
75 /* Run the CPU from PLL1 and UART from PLL2 */
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
95 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
100 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
105 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
110 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
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| /openbmc/linux/kernel/sched/ |
| H A D | deadline.c | 1 // SPDX-License-Identifier: GPL-2.0
24 * guard against timer DoS.
72 return &rq->dl; in dl_rq_of_se()
77 return !RB_EMPTY_NODE(&dl_se->rb_node); in on_dl_rq()
83 return dl_se->pi_se; in pi_of()
107 return &cpu_rq(i)->rd->dl_bw; in dl_bw_of()
112 struct root_domain *rd = cpu_rq(i)->rd; in dl_bw_cpus()
118 if (cpumask_subset(rd->span, cpu_active_mask)) in dl_bw_cpus()
119 return cpumask_weight(rd->span); in dl_bw_cpus()
123 for_each_cpu_and(i, rd->span, cpu_active_mask) in dl_bw_cpus()
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| /openbmc/linux/Documentation/dev-tools/ |
| H A D | kfence.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Kernel Electric-Fence (KFENCE)
7 Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety
8 error detector. KFENCE detects heap out-of-bounds access, use-after-free, and
9 invalid-free errors.
15 non-production test workloads. One way to quickly achieve a large enough total
19 -----
26 ``kfence.sample_interval`` to non-zero value), configure the kernel with::
44 The sample interval controls a timer that sets up KFENCE allocations. By
45 default, to keep the real sample interval predictable, the normal timer also
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| /openbmc/linux/kernel/power/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 suspend-to-RAM state (e.g. the ACPI S3 state).
30 user-space before invoking suspend. There's a run-time switch
32 This setting changes the default for the run-tim switch. Say Y
60 for suspend states like suspend-to-RAM (STR) often don't work very
72 <file:Documentation/power/swsusp-and-swap-files.rst>).
75 meantime you cannot use the swap partition(s)/file(s) involved in
100 The default resume partition is the partition that the suspend-
101 to-disk implementation will look for a suspended disk image.
135 non-zero numbered CPU, it may define ARCH_SUSPEND_NONZERO_CPU. This
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| /openbmc/linux/drivers/usb/musb/ |
| H A D | tusb6010.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * - Driver assumes that interface to external host (main CPU) is
27 #include <linux/dma-mapping.h>
51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
71 rev = musb->tusb_revision; in tusb_print_revision()
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
123 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
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| /openbmc/linux/drivers/power/reset/ |
| H A D | at91-sama5d2_shdwc.c | 2 * Atmel SAMA5D2-Compatible Shutdown Controller (SHDWC) driver.
8 * Evolved from driver at91-poweroff.c.
15 * - addition to status of other wake-up inputs [1 - 15]
16 * - Analog Comparator wake-up alarm
17 * - Serial RX wake-up alarm
18 * - low power debouncer
50 #define AT91_SHDW_WUIR 0x0c /* Shutdown Wake-up Inputs Register */
58 #define SHDW_WK_PIN(reg, cfg) ((reg) & AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
59 #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1)
60 #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1)
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| /openbmc/linux/Documentation/admin-guide/pm/ |
| H A D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>`
8 CPU Idle Time Management
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
37 software as individual single-core processors. In other words, a CPU is an
43 program) at a time, it is a CPU. In that case, if the hardware is asked to
46 Second, if the processor is multi-core, each core in it is able to follow at
61 Finally, each core in a multi-core processor may be able to follow more than one
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| /openbmc/linux/arch/x86/kernel/acpi/ |
| H A D | boot.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
80 * ->device_hotplug_lock
81 * ->acpi_ioapic_lock
82 * ->ioapic_lock
84 * ->acpi_ioapic_lock
85 * ->ioapic_mutex
86 * ->ioapic_lock
91 /* --------------------------------------------------------------------------
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| /openbmc/linux/drivers/acpi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
18 Linux requires an ACPI-compliant platform (hardware/firmware),
19 and assumes the presence of OS-directed configuration and power
25 the Plug-and-Play BIOS specification (PnP BIOS), the
35 ACPI is an open industry specification originally co-developed by
36 Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. Currently,
67 Enable in-kernel debugging of AML facilities: statistics,
125 This option enables a DMI-based quirk for the above Dell machine (so
178 performs user-defined actions such as shutting down the system.
179 This is necessary for software-controlled poweroff.
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| /openbmc/linux/drivers/tty/ |
| H A D | mips_ejtag_fdc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
25 #include <linux/timer.h>
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
137 * @poll_timer: Timer for polling for interrupt events when @irq < 0.
144 unsigned int cpu; member
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
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| /openbmc/u-boot/doc/ |
| H A D | README.iscsi | 1 # iSCSI booting with U-Boot and iPXE
5 U-Boot has only a reduced set of supported network protocols. The focus for
13 These protocols are insecure. The client cannot validate the authenticity
14 of the contacted servers. And the server cannot verify the identity of the
34 An alternative to implementing these protocols in U-Boot is to use an existing
35 software that can run on top of U-Boot. iPXE[1] is the "swiss army knife" of
40 run by U-Boot.
44 U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
46 U-Boot.
56 uses the ConnectController boot service of U-Boot to request U-Boot to connect a
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| /openbmc/linux/Documentation/scheduler/ |
| H A D | sched-deadline.rst | 12 3. Scheduling Real-Time Tasks
18 4.1 System-wide settings
22 5. Tasks CPU affinity
33 system behavior. As for -rt (group) scheduling, it is assumed that root users
50 ------------------
63 (clearly, if the system is overloaded this guarantee cannot be respected).
70 with the "traditional" real-time task model (see Section 3) can effectively
76 - Each SCHED_DEADLINE task is characterized by the "runtime",
79 - The state of the task is described by a "scheduling deadline", and
82 - When a SCHED_DEADLINE task wakes up (becomes ready for execution),
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| /openbmc/linux/kernel/ |
| H A D | softirq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Rewritten. Old one was good in 2.2, but in 2.3 it was immoral. --ANK (990903)
20 #include <linux/cpu.h>
37 - No shared variables, all the data are CPU local.
38 - If a softirq needs serialization, let it serialize itself
40 - Even if softirq is serialized, only local cpu is marked for
41 execution. Hence, we get something sort of weak cpu binding.
46 - NET RX softirq. It is multithreaded and does not require
48 - NET TX softirq. It kicks software netdevice queues, hence
51 - Tasklets: serialized wrt itself.
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| /openbmc/linux/arch/arm/mach-omap1/ |
| H A D | pm.c | 2 * linux/arch/arm/mach-omap1/pm.c
47 #include <linux/cpu.h>
55 #include <linux/soc/ti/omap1-io.h>
57 #include <linux/omap-dma.h>
58 #include <clocksource/timer-ti-dm.h>
91 return -EINVAL; in idle_store()
129 * tests above as soon as drivers, timer and DMA code have been fixed. in omap1_pm_idle()
163 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, in omap_pm_wakeup_setup()
166 * wake up to a GPIO interrupt. in omap_pm_wakeup_setup()
263 /* (Step 3 removed - we now allow deep sleep by default) */ in omap1_pm_suspend()
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| /openbmc/linux/arch/ia64/kernel/ |
| H A D | mca.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
21 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
27 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
31 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
37 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
38 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
42 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
45 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
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