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/openbmc/linux/arch/parisc/kernel/
H A Dperf_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
46 sync ; follow ERS
100 ;* %r24 - original DR2 value
101 ;* %r1 - scratch
102 ;* %r29 - scratch
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
132 ; Cacheline start (32-byte cacheline)
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/openbmc/qemu/tests/qemu-iotests/
H A D257.out2 === Mode bitmap; Bitmap Sync never with simulated failure ===
4 --- Preparing image & VM ---
6 {"execute": "blockdev-add", "arguments": {"driver": "qcow2", "file": {"driver": "file", "filename":…
9 --- Write #0 ---
11 write -P0x49 0x0000000 0x10000
13 write -P0x6c 0x0100000 0x10000
15 write -P0x6f 0x2000000 0x10000
17 write -P0x76 0x3ff0000 0x10000
23 --- Reference Backup #0 ---
26 {"execute": "job-dismiss", "arguments": {"id": "bdc-file-job"}}
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H A D0564 # Tests for drive-backup
37 optargs = optargs + ['-o', '%s=%s' % (k,v)]
38 args = ['create', '-f', fmt] + optargs + [fullname, size]
50 iotests.qemu_io('-c', 'write -P%s %s %s' % pattern, img)
58 qemu_img('create', '-f', iotests.imgfmt,
59 '-o', 'backing_file=%s' % backing_img, '-F', 'raw', test_img)
60 qemu_io('-c', 'write -P0x41 0 512', test_img)
61 qemu_io('-c', 'write -P0xd5 1M 32k', test_img)
62 qemu_io('-c', 'write -P0xdc 32M 124k', test_img)
63 qemu_io('-c', 'write -P0xdc 67043328 64k', test_img)
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H A D0554 # Tests for drive-backup and blockdev-backup
31 blockdev_target_img = os.path.join(iotests.test_dir, 'blockdev-target.img')
36 qemu_img('create', '-f', iotests.imgfmt, test_img, str(image_len))
37 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0x11 0 64k', test_img)
38 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0x00 64k 128k', test_img)
39 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0x22 162k 32k', test_img)
40 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0xd5 1M 32k', test_img)
41 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0xdc 32M 124k', test_img)
42 qemu_io('-f', iotests.imgfmt, '-c', 'write -P0x33 67043328 64k', test_img)
50 qemu_img('create', '-f', iotests.imgfmt, blockdev_target_img, str(image_len))
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/openbmc/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
101 /* Write Register 4 */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
93 /* Write Register 4 */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
105 /* Write Register 2 (Interrupt Vector) */
107 /* Write Register 3 (Receive Parameters and Control) */
109 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
120 /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/openbmc/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
67 /* Write Register 4 */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
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/openbmc/linux/fs/
H A Dsync.c1 // SPDX-License-Identifier: GPL-2.0
3 * High-level sync()-related operations
19 #include <linux/backing-dev.h>
26 * Write out and wait upon all dirty data associated with this
38 WARN_ON(!rwsem_is_locked(&sb->s_umount)); in sync_filesystem()
41 * No point in syncing out anything if the filesystem is read-only. in sync_filesystem()
51 * methods call sync_dirty_buffer() and thus effectively write one block in sync_filesystem()
55 if (sb->s_op->sync_fs) { in sync_filesystem()
56 ret = sb->s_op->sync_fs(sb, 0); in sync_filesystem()
60 ret = sync_blockdev_nowait(sb->s_bdev); in sync_filesystem()
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/openbmc/u-boot/board/freescale/mx6sabresd/
H A DREADME1 How to use and build U-Boot on mx6sabresd
2 -----------------------------------------
14 -------------------------------
24 This will generate the SPL and u-boot-dtb.img binaries.
26 - Flash the SPL binary into the SD card:
28 $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
30 - Flash the u-boot-dtb.img binary into the SD card:
32 $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
36 --------------------
42 This will generate the SPL and u-boot-dtb.img binaries.
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S35 /* use invalidate-all bit in HID0 */
68 * Write any modified data cache blocks out to memory
70 * This is a no-op on the 601.
75 li r5,CACHE_LINE_SIZE-1
86 sync /* wait for dcbst's to get to ram */
91 sync /* additional sync needed on g4 */
95 * Write any modified data cache blocks out to memory.
102 li r5,CACHE_LINE_SIZE-1
105 add r4,r4,r5 /* r4 += cache_line_size-1 */
110 sync
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/openbmc/u-boot/board/freescale/mx6sabreauto/
H A DREADME1 How to use and build U-Boot on mx6sabreauto
2 -------------------------------------------
12 This will generate the SPL and u-boot-dtb.img binaries.
14 - Flash the SPL binary into the SD card:
16 $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
18 - Flash the u-boot-dtb.img binary into the SD card:
20 $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
23 -----------------------
25 Write in mx6sabreauto_defconfig the following define below:
35 This will generate the SPL image called SPL and the u-boot-dtb.img.
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/openbmc/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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/openbmc/linux/include/uapi/linux/
H A Ddma-buf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * struct dma_buf_sync - Synchronize with CPU access.
29 * possible to guarantee coherency between the CPU-visible map and underlying
35 * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
37 * DMA_BUF_SYNC_END and the same read/write flags.
45 * follow-up work is not submitted to GPU or other device driver until
89 * struct dma_buf_export_sync_file - Get a sync_file from a dma-buf
92 * current set of fences on a dma-buf file descriptor as a sync_file. CPU
93 * waits via poll() or other driver-specific mechanisms typically wait on
94 * whatever fences are on the dma-buf at the time the wait begins. This
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/openbmc/u-boot/board/gateworks/gw_ventana/
H A DREADME1 U-Boot for the Gateworks Ventana Product Family boards
3 This file contains information for the port of U-Boot to the Gateworks
7 is supported by a single bootloader build by using a common SPL and U-Boot
13 ---------------------------------
19 will build the following artifacts from U-Boot source:
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
22 The DRAM controller, loads u-boot.img from the detected boot device,
25 - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
29 --------
31 To build U-Boot for the Gateworks Ventana product family:
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/openbmc/linux/fs/ntfs/
H A Dmft.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mft.h - Defines for mft record handling in NTFS Linux kernel driver.
4 * Part of the Linux-NTFS project.
6 * Copyright (c) 2001-2004 Anton Altaparmakov
33 * flush_dcache_mft_record_page - flush_dcache_page() for mft records
43 flush_dcache_page(ni->page); in flush_dcache_mft_record_page()
49 * mark_mft_record_dirty - set the mft record and the page containing it dirty
66 MFT_RECORD *m, int sync);
68 extern int write_mft_record_nolock(ntfs_inode *ni, MFT_RECORD *m, int sync);
71 * write_mft_record - write out a mapped (extent) mft record
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/openbmc/linux/include/linux/firmware/intel/
H A Dstratix10-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
9 #include <linux/arm-smccc.h>
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
31 * STD call starts a operation which can be preempted by a non-secure
81 * Sync call used by service driver at EL1 to request the FPGA in EL3 to
88 * a2-7: not used.
92 * a1-3: not used.
108 * a3-7: not used.
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/openbmc/linux/drivers/power/supply/
H A Dda9150-fg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DA9150 Fuel-Gauge Driver
22 #include <linux/devm-helpers.h>
61 /* QIF Sync Timeout */
99 da9150_read_qif(fg->da9150, read_addr, size, buf); in da9150_fg_read_attr()
114 /* Set QIF code (WRITE mode) */ in da9150_fg_write_attr()
121 da9150_write_qif(fg->da9150, write_addr, size, buf); in da9150_fg_write_attr()
124 /* Trigger QIF Sync to update QIF readable data */
130 mutex_lock(&fg->io_lock); in da9150_fg_read_sync_start()
132 /* Check if QIF sync already requested, and write to sync if not */ in da9150_fg_read_sync_start()
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/openbmc/u-boot/board/Barix/ipam390/
H A DREADME.ipam3905 In the context of U-Boot, the board is booted in three stages. The initial
19 spl code starts the u-boot image
29 it allows for additional flexibility (run-time detect of board revision,
34 run "tools/buildman/buildman -k ipam390" in the u-boot source tree.
35 Once this build completes you will have a ../current/ipam390/u-boot.ais file
41 Assuming that the network is configured and enabled and the u-boot.ais file
44 U-Boot > print upd_uboot
45 upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize}
46 U-Boot >
47 U-Boot > run upd_uboot
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/openbmc/linux/Documentation/admin-guide/cgroup-v1/
H A Dblkio-controller.rst22 -----------------------------
33 mount -t cgroup -o blkio none /sys/fs/cgroup/blkio
98 --------------------------------
106 see Documentation/block/bfq-iosched.rst.
110 weight. For more details, see Documentation/block/bfq-iosched.rst.
152 are further divided by the type of operation - read or write, sync
159 are further divided by the type of operation - read or write, sync
173 the type of operation - read or write, sync or async. First two fields
186 (there might be a time lag here due to re-ordering of requests by the
188 devices too. This time is further divided by the type of operation -
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/openbmc/linux/tools/testing/selftests/arm64/mte/
H A Dcheck_buffer_fill.c1 // SPDX-License-Identifier: GPL-2.0
17 1, 555, 1033, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE,
18 /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0
80 mte_initialize_current_context(mode, (uintptr_t)ptr, -underflow_range); in check_buffer_underflow_by_byte()
83 for (j = sizes[i] - 1; (j >= -underflow_range) && in check_buffer_underflow_by_byte()
84 (!cur_mte_cxt.fault_valid); j--) { in check_buffer_underflow_by_byte()
104 if (cur_mte_cxt.fault_valid == true || last_index != -underflow_range) { in check_buffer_underflow_by_byte()
109 und_ptr = (char *) MT_CLEAR_TAG((size_t) ptr - underflow_range); in check_buffer_underflow_by_byte()
124 * The imprecise fault is checked after the write to the buffer, in check_buffer_underflow_by_byte()
137 if (!cur_mte_cxt.fault_valid || (last_index != (-1))) { in check_buffer_underflow_by_byte()
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/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
65 2. sync common
85 4. read async non-muxed
96 5. read sync muxed
107 6. read sync non-muxed
118 7. write async muxed
131 8. write async non-muxed
144 9. write sync muxed
157 10. write sync non-muxed
/openbmc/linux/drivers/staging/pi433/Documentation/
H A Dpi433.txt28 kfifo. With each write request of an application, the passed in data and the
60 the calls open, ioctl, read, write and close.
64 ----------------
67 PI433_IOC_RD_TX_CFG - get the transmission parameters from the driver
68 PI433_IOC_WR_TX_CFG - set the transmission parameters
69 PI433_IOC_RD_RX_CFG - get the receiving parameters from the driver
70 PI433_IOC_WR_RX_CFG - set the receiving parameters
86 FSK - frequency shift key
87 OOK - On-Off-key
89 shapingOff - no shaping
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
18 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status()
20 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status()
24 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); in ecc_print_status()
28 printf(" Multiple-Bit Error Interrupt Enable: %d\n", in ecc_print_status()
29 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); in ecc_print_status()
30 printf(" Single-Bit Error Interrupt Enable: %d\n", in ecc_print_status()
31 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); in ecc_print_status()
33 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); in ecc_print_status()
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