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/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0
108 switch (div) { in meson_vid_pll_set()
239 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
250 VCLK2_DIV_MASK, (55 - 1)); in meson_venci_cvbs_clock_config()
252 /* select vid_pll for vclk2 */ in meson_venci_cvbs_clock_config()
258 /* select vclk_div1 for enci */ in meson_venci_cvbs_clock_config()
261 /* select vclk_div1 for vdac */ in meson_venci_cvbs_clock_config()
375 switch (od) { in pll_od_to_reg()
414 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()
432 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
20 u32 cpu = readl(&mscmir->cpxtype); in get_cpu_rev()
35 return -1; in get_pllfreq()
57 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
97 u32 freq = 0; in get_mcu_main_clk() local
107 switch (sysclk_sel) { in get_mcu_main_clk()
109 freq = FIRC_CLK_FREQ; in get_mcu_main_clk()
112 freq = XOSC_CLK_FREQ; in get_mcu_main_clk()
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmax98090.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
252 switch (reg) { in max98090_volatile_register()
265 switch (reg) { in max98090_readable_register()
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
[all …]
H A Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
196 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
197 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
198 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
214 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_sysclk_check()
218 switch (adav80x->clk_src) { in adav80x_dapm_sysclk_check()
232 return strcmp(source->name, clk) == 0; in adav80x_dapm_sysclk_check()
238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in adav80x_dapm_pll_check()
[all …]
H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 /* -54dB */
34 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
35 /* -52.5dB to 15dB */
36 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
41 /* -78dB to 12dB */
42 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
51 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
52 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
53 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
[all …]
H A Drt1019.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt1019.c -- RT1019 ALSA SoC audio amplifier driver
25 #include <sound/soc-dapm.h>
61 switch (reg) { in rt1019_volatile_register()
77 switch (reg) { in rt1019_readable_register()
108 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
122 SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel),
128 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in r1019_dac_event()
130 switch (event) { in r1019_dac_event()
159 struct snd_soc_component *component = dai->component; in rt1019_hw_params()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c33 u32 freq; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
74 switch (pll) { in read_pll()
77 sclk = device->crystal; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
112 switch (ssrc & 0x00000003) { in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
136 switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) { in read_mem()
[all …]
H A Dgf100.c33 u32 freq; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
72 switch (pll) { in read_pll()
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
46 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
53 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
64 pllm = data->pll_m - 1; in configure_mult_div()
65 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; in configure_mult_div()
68 if (data->pll == MAIN_PLL) in configure_mult_div()
69 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
71 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
76 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ in configure_mult_div()
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dfc0011.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
22 FC11_REG_VCOSEL, /* VCO select */
39 FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
40 FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
70 struct i2c_msg msg = { .addr = priv->addr, in fc0011_writereg()
73 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0011_writereg()
74 dev_err(&priv->i2c->dev, in fc0011_writereg()
77 return -EIO; in fc0011_writereg()
87 { .addr = priv->addr, in fc0011_readreg()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
25 switch (frac_pll) { in decode_frac_pll()
27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg); in decode_frac_pll()
88 switch (sscg_pll) { in decode_sscg_pll()
98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()
99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
44 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
54 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
60 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
62 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
11 #include <asm/mach-imx/sys_proto.h>
29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
43 u32 freq = 0; in get_mcu_main_clk() local
45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
54 switch (sysclk_sel) { in get_mcu_main_clk()
56 freq = FASE_CLK_FREQ; in get_mcu_main_clk()
[all …]
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-dai-i2s.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "mt8186-afe-clk.h"
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-gpio.h"
14 #include "mt8186-interconnection.h"
88 return -EINVAL; in get_i2s_id_by_name()
94 struct mt8186_afe_private *afe_priv = afe->platform_priv; in get_i2s_priv_by_name()
100 return afe_priv->dai_priv[dai_id]; in get_i2s_priv_by_name()
120 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); in mt8186_i2s_hd_get()
121 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; in mt8186_i2s_hd_get()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dad7192.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
32 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
33 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
34 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
35 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
36 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
37 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
38 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
39 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
[all …]
/openbmc/u-boot/board/freescale/mpc8572ds/
H A DREADME2 --------
3 MPC8572DS is a high-performance computing, evaluation and development platform
6 Building U-Boot
7 -----------
12 -----------
14 locations can be swapped using the dip-switch SW9[1:2].
20 ----------
22 0xe800_0000 - 0xebff_ffff Alternate bank 64MB
23 0xec00_0000 - 0xefff_ffff Boot bank 64MB
25 0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB
[all …]
/openbmc/linux/drivers/media/radio/
H A Dradio-cadet.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* radio-cadet.c - A video4linux driver for the ADS Cadet AM/FM Radio Card
17 * 2000-04-29 Russell Kroll <rkroll@exploits.org>
20 * 2001-01-10 Russell Kroll <rkroll@exploits.org>
24 * 2002-01-17 Adam Belay <ambx1@neo.rr.com>
27 * 2003-01-31 Alan Cox <alan@lxorguk.ukuu.org.uk>
30 * 2006-07-30 Hans J. Koch <koch@hjk-az.de>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-ioctl.h>
45 #include <media/v4l2-ctrls.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rt6245-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
31 it will be treat as a default-on power.
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A Dt102xqds.c1 // SPDX-License-Identifier: GPL-2.0+
30 struct cpu_type *cpu = gd->arch.cpu; in checkboard()
31 static const char *const freq[] = {"100", "125", "156.25", "100.0"}; in checkboard() local
35 printf("Board: %sQDS, ", cpu->name); in checkboard()
37 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); in checkboard()
68 printf("Clock1=%sMHz ", freq[clock]); in checkboard()
70 printf("Clock2=%sMHz\n", freq[clock]); in checkboard()
81 puts("PCA: failed to select proper channel\n"); in select_i2c_ch_pca9547()
94 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane_to_slot()
102 switch (srds_prtcl_s1) { in board_mux_lane_to_slot()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk322x.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3228-cru.h>
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
[all …]
H A Dclk_rk3036.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3036-cru.h>
27 ((input_rate) / (output_rate) - 1);
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
[all …]
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
[all …]
/openbmc/linux/arch/m68k/mac/
H A Dmacboing.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mac bong noise generator. Note - we ought to put a boingy noise
6 * ----------------------------------------------------------------------
10 * Juergen Mellinger (juergen.mellinger@t-online.de)
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
78 switch ( macintosh_config->ident ) in mac_init_asc()
106 * current location of the Apple Sound Chip--ASC--in other Macs.) The in mac_init_asc()
111 * Macintosh models have 16-bit audio input and output capability in mac_init_asc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
[all …]

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