Searched +full:sun4i +full:- +full:a10 +full:- +full:system +full:- +full:control (Results 1 – 25 of 33) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.0+3 ---4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A10 System Control10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>15 by a regular node for the SRAM controller itself, with sub-nodes19 "#address-cells":22 "#size-cells":[all …]
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",91 .compatible = "allwinner,sun4i-a10-sram-c1",95 .compatible = "allwinner,sun4i-a10-sram-d",99 .compatible = "allwinner,sun50i-a64-sram-c",120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()122 for_each_child_of_node(sram_dev->of_node, sram_node) { in sunxi_sram_show()123 if (!of_device_is_compatible(sram_node, "mmio-sram")) in sunxi_sram_show()[all …]
2 * Copyright 2012-2015 Maxime Ripard4 * Maxime Ripard <maxime.ripard@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/clock/sun5i-ccu.h>46 #include <dt-bindings/dma/sun4i-a10.h>47 #include <dt-bindings/reset/sun5i-ccu.h>50 interrupt-parent = <&intc>;51 #address-cells = <1>;52 #size-cells = <1>;55 #address-cells = <1>;[all …]
5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/thermal/thermal.h>45 #include <dt-bindings/dma/sun4i-a10.h>46 #include <dt-bindings/clock/sun4i-a10-ccu.h>47 #include <dt-bindings/reset/sun4i-a10-ccu.h>50 #address-cells = <1>;51 #size-cells = <1>;52 interrupt-parent = <&intc>;59 #address-cells = <1>;60 #size-cells = <1>;[all …]
4 * Maxime Ripard <maxime.ripard@free-electrons.com>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>46 #include <dt-bindings/thermal/thermal.h>47 #include <dt-bindings/dma/sun4i-a10.h>48 #include <dt-bindings/clock/sun7i-a20-ccu.h>49 #include <dt-bindings/reset/sun4i-a10-ccu.h>50 #include <dt-bindings/pinctrl/sun4i-a10.h>53 interrupt-parent = <&gic>;54 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>11 #address-cells = <1>;12 #size-cells = <1>;13 interrupt-parent = <&intc>;16 osc24M: clk-24M {17 #clock-cells = <0>;18 compatible = "fixed-clock";19 clock-frequency = <24000000>;[all …]
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/interrupt-controller/arm-gic.h>45 #include <dt-bindings/clock/sun6i-rtc.h>46 #include <dt-bindings/clock/sun8i-de2.h>47 #include <dt-bindings/clock/sun8i-r40-ccu.h>48 #include <dt-bindings/clock/sun8i-tcon-top.h>49 #include <dt-bindings/reset/sun8i-r40-ccu.h>50 #include <dt-bindings/reset/sun8i-de2.h>51 #include <dt-bindings/thermal/thermal.h>[all …]
4 * This file is dual-licensed: you can use it either under the terms43 #include "sunxi-h3-h5.dtsi"44 #include <dt-bindings/thermal/thermal.h>47 cpu0_opp_table: opp-table-cpu {48 compatible = "operating-points-v2";49 opp-shared;51 opp-648000000 {52 opp-hz = /bits/ 64 <648000000>;53 opp-microvolt = <1040000 1040000 1300000>;54 clock-latency-ns = <244144>; /* 8 32k periods */[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun6i-rtc.h>48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>52 interrupt-parent = <&gic>;53 #address-cells = <1>;54 #size-cells = <1>;[all …]
5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/interrupt-controller/arm-gic.h>45 #include <dt-bindings/clock/sun6i-rtc.h>46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>48 #include <dt-bindings/clock/sun8i-de2.h>51 #address-cells = <1>;52 #size-cells = <1>;53 interrupt-parent = <&gic>;56 #address-cells = <1>;[all …]
9 # later. See the COPYING file in the top-level directory.31 return 1 if x == 0 else 2**(x - 1).bit_length()53 failure_message='Kernel panic - not syncing',89 process.run("rpm2cpio %s | cpio -id %s" % (rpm, path), shell=True)113 self.vm.add_args('-kernel', kernel_path,114 '-append', kernel_command_line)122 :avocado: tags=machine:xlnx-versal-virt127 images_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'128 'bionic-updates/main/installer-arm64/'130 kernel_url = images_url + 'netboot/ubuntu-installer/arm64/linux'[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>24 #include "sun4i-ss.h"50 .cra_driver_name = "md5-sun4i-ss",77 .cra_driver_name = "sha1-sun4i-ss",99 .cra_driver_name = "cbc-aes-sun4i-ss",120 .cra_driver_name = "ecb-aes-sun4i-ss",142 .cra_driver_name = "cbc-des-sun4i-ss",163 .cra_driver_name = "ecb-des-sun4i-ss",[all …]
1 // SPDX-License-Identifier: GPL-2.0+7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c8 * and earlier U-Boot Allwinner A10 SPL work10 * (C) Copyright 2007-201268 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()[all …]
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM6413 like A10/A13/A20.87 ---help---100 ---help---102 as the original A10 (mach-sun4i).106 ---help---108 separate ahb reset control registers, custom pmic bus, new style113 ---help---116 not have official open-source DRAM initialization code, but can122 ---help---[all …]
4 * This file is dual-licensed: you can use it either under the terms43 #include "sunxi-h3-h5.dtsi"47 compatible = "operating-points-v2";48 opp-shared;51 opp-hz = /bits/ 64 <648000000>;52 opp-microvolt = <1040000 1040000 1300000>;53 clock-latency-ns = <244144>; /* 8 32k periods */57 opp-hz = /bits/ 64 <816000000>;58 opp-microvolt = <1100000 1100000 1300000>;59 clock-latency-ns = <244144>; /* 8 32k periods */[all …]
6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>48 #include <dt-bindings/clock/sun8i-de2.h>49 #include <dt-bindings/clock/sun8i-r-ccu.h>50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>51 #include <dt-bindings/reset/sun8i-de2.h>52 #include <dt-bindings/reset/sun8i-r-ccu.h>55 interrupt-parent = <&gic>;56 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 #include <arm/allwinner/sunxi-h3-h5.dtsi>6 #include <dt-bindings/thermal/thermal.h>10 #address-cells = <1>;11 #size-cells = <0>;14 compatible = "arm,cortex-a53";17 enable-method = "psci";19 clock-latency-ns = <244144>; /* 8 32k periods */20 #cooling-cells = <2>;24 compatible = "arm,cortex-a53";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/clock/sun50i-h6-ccu.h>6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>7 #include <dt-bindings/clock/sun6i-rtc.h>8 #include <dt-bindings/clock/sun8i-de2.h>9 #include <dt-bindings/clock/sun8i-tcon-top.h>10 #include <dt-bindings/reset/sun50i-h6-ccu.h>11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>12 #include <dt-bindings/reset/sun8i-de2.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only22 #define DRV_NAME "ahci-sunxi"118 if (--timeout == 0) { in ahci_sunxi_phy_init()120 return -EIO; in ahci_sunxi_phy_init()133 if (--timeout == 0) { in ahci_sunxi_phy_init()135 return -EIO; in ahci_sunxi_phy_init()150 struct ahci_host_priv *hpriv = ap->host->private_data; in ahci_sunxi_start_engine()156 * User's Guide document (TMS320C674x/OMAP-L1x Processor in ahci_sunxi_start_engine()158 * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR), in ahci_sunxi_start_engine()173 * transmit (system bus read, device write) operation. [...] in ahci_sunxi_start_engine()[all …]
1 .. SPDX-License-Identifier: GPL-2.012 - Exynos413 - Exynos514 - STIH4xx HDMI CEC15 - V4L2 adv7511 (same HW, but a different driver from the drm adv7511)16 - stm3217 - Allwinner A10 (sun4i)18 - Raspberry Pi19 - dw-hdmi (Synopsis IP)20 - amlogic (meson ao-cec and ao-cec-g12a)[all …]
4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>34 #include "sun4i-emac.h"36 #define DRV_NAME "sun4i-emac"41 static int debug = -1; /* defaults above */;52 * The EMAC uses an address register to control where data written57 * protect the system, but the calls themselves save the address108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()110 if (db->speed == SPEED_100) in emac_update_speed()112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()[all …]
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1 # SPDX-License-Identifier: GPL-2.0-only24 bool "Altera Arria10 DevKit System Resource chip"29 Support for the Altera Arria10 DevKit MAX5 System Resource chip35 bool "Altera SOCFPGA System Manager"39 Select this to get System Manager support for all Altera branded40 SOCFPGAs. The SOCFPGA System Manager handles all SOCFPGAs by45 tristate "Active-semi ACT8945A"50 Support for the ACT8945A PMIC from Active-semi. This device51 features three step-down DC/DC converters and four low-dropout63 Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.[all …]
1 # SPDX-License-Identifier: GPL-2.0-only13 dynamic device discovery; some are even write-only or read-only.17 chips, analog to digital (and d-to-a) converters, and more.44 If your system has an master-capable SPI controller (which56 by providing a high-level interface to send memory-like commands.145 supports spi-mem interface.215 that adds the capability to allow the driver to control chip select221 With a few GPIO pins, your system can bitbang the SPI protocol.224 this code to manage the per-word or per-transfer accesses to the254 Flash over 1/2/4-bit wide bus. Enable this option if you have a[all …]
1 # SPDX-License-Identifier: GPL-2.0-only20 be allowed to plug one or more RTCs to your system. You will26 bool "Set system time from RTC on startup and resume"29 If you say yes here, the system time (wall clock) will be set using34 string "RTC used to set the system time"38 The RTC device that will be used to (re)initialize the system39 clock, usually rtc0. Initialization is done when the system44 This clock should be battery-backed, so that it reads the correct45 time when the system boots from a power-off state. Otherwise, your46 system will need an external clock source (like an NTP server).[all …]