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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
17 the others for outputs (fsin1 and fsin2). Strobe input to start the current
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
[all …]
/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
31 * @clk_pol: Pixel clock polarity
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
33 * @hs_pol: Horizontal synchronization polarity
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dintel,ixp4xx-expansion-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
18 intel,ixp4xx-eb-t1:
23 intel,ixp4xx-eb-t2:
28 intel,ixp4xx-eb-t3:
29 description: Strobe timing, extend strobe phase with n cycles.
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/openbmc/linux/include/media/
H A Dv4l2-mediabus.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/v4l2-mediabus.h>
46 * Signal polarity flags
60 /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
62 /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
64 /* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
71 /* Clock non-continuous mode support. */
77 * struct v4l2_mbus_config_mipi_csi2 - MIPI CSI-2 data bus configuration
82 * @lane_polarities: polarity of the lanes. The order is the same of
94 * struct v4l2_mbus_config_parallel - parallel data bus configuration
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
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/openbmc/linux/drivers/parport/
H A Dieee1284_ops.c1 // SPDX-License-Identifier: GPL-2.0
2 /* IEEE-1284 operations for parport.
5 * they are used by the low-level drivers. If they have a special way
7 * the function pointers in port->ops); if not, they can just use these
13 * Fixed AUTOFD polarity in ecp_forward_to_reverse(). Fred Barnes, 1999
31 * One-way data transfer functions. *
43 struct pardevice *dev = port->physport->cad; in parport_ieee1284_write_compat()
47 if (port->irq != PARPORT_IRQ_NONE) { in parport_ieee1284_write_compat()
52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
56 unsigned long expire = jiffies + dev->timeout; in parport_ieee1284_write_compat()
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-counter3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
16 MTCLKA-MTCLKB:
20 MTCLKC-MTCLKD:
26 Contact: linux-iio@vger.kernel.org
33 Contact: linux-iio@vger.kernel.org
39 Contact: linux-iio@vger.kernel.org
45 Contact: linux-iio@vger.kernel.org
52 Contact: linux-iio@vger.kernel.org
59 Contact: linux-iio@vger.kernel.org
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/openbmc/linux/drivers/auxdisplay/
H A Dpanel.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 # see Documentation/kbuild/kconfig-language.rst.
22 This is the base system for character-based LCD displays.
31 This is the core support for single-line character displays, to be
66 and built-in as well (Y).
121 If you have a Crystalfontz 128x64 2-color LCD, cfag12864b Series,
125 check Documentation/admin-guide/auxdisplay/cfag12864b.rst
150 Be careful modifying this value to a very high value:
211 Say Y here if you have an HD44780 or KS-0074 LCD connected to your
212 parallel port. This driver also features 4 and 6-key keypads. The LCD
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/openbmc/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-sapphire.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "dt-bindings/pwm/pwm.h"
7 #include "dt-bindings/input/input.h"
9 #include "rk3399-opp.dtsi"
12 compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "clkin_gmac";
[all …]
H A Drk3399pro-vmarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/pwm/pwm.h>
13 compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
20 vcc3v3_pcie: vcc-pcie-regulator {
21 compatible = "regulator-fixed";
22 enable-active-high;
24 pinctrl-names = "default";
25 pinctrl-0 = <&pcie_pwr>;
[all …]
H A Drk3399-leez-p710.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
11 #include "rk3399-opp.dtsi"
24 stdout-path = "serial2:1500000n8";
27 clkin_gmac: external-gmac-clock {
28 compatible = "fixed-clock";
29 clock-frequency = <125000000>;
[all …]
H A Drk3399-hugsun-x99.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /dts-v1/;
3 #include <dt-bindings/pwm/pwm.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "rk3399-opp.dtsi"
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
[all …]
H A Drk3399-nanopi4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * RK3399-based FriendlyElec boards device tree source
14 /dts-v1/;
15 #include <dt-bindings/input/linux-event-codes.h>
17 #include "rk3399-opp.dtsi"
27 stdout-path = "serial2:1500000n8";
30 clkin_gmac: external-gmac-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <125000000>;
33 clock-output-names = "clkin_gmac";
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
[all …]
H A Drk3399-firefly.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/usb/pd.h>
12 #include "rk3399-opp.dtsi"
15 model = "Firefly-RK3399 Board";
16 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
25 stdout-path = "serial2:1500000n8";
[all …]
H A Drk3399-rock960.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "rk3399-opp.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
19 sdio_pwrseq: sdio-pwrseq {
20 compatible = "mmc-pwrseq-simple";
22 clock-names = "ext_clock";
23 pinctrl-names = "default";
24 pinctrl-0 = <&wifi_enable_h>;
25 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
28 vcc12v_dcin: vcc12v-dcin {
[all …]
H A Drk3399-puma.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3399-opp.dtsi"
16 compatible = "gpio-leds";
17 pinctrl-names = "default";
18 pinctrl-0 = <&module_led_pin>;
20 module_led: led-0 {
23 linux,default-trigger = "heartbeat";
24 panic-indicator;
28 extcon_usb3: extcon-usb3 {
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-firefly.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-ddr3-1600.dtsi"
13 model = "Firefly-RK3399 Board";
14 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
17 stdout-path = &uart2;
18 u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
22 compatible = "pwm-backlight";
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
[all …]
/openbmc/linux/drivers/media/v4l2-core/
H A Dv4l2-fwnode.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * formerly was located in v4l2-of.c.
11 * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
31 #include "v4l2-subdev-priv.h"
45 "MIPI CSI-2 C-PHY",
49 "MIPI CSI-1",
57 "MIPI CSI-2 D-PHY",
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Daddi_apci_1500.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
23 * PCI Bar 0 Register map (devpriv->amcc)
28 * PCI Bar 1 Register map (dev->iobase)
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