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/openbmc/linux/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
H A Dpipeline.c49 static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage);
260 /* @brief Add a stage to pipeline.
263 * @param[in] stage_desc The description of the stage
264 * @param[out] stage The successor of the stage.
267 * Add a new stage to a non-NULL pipeline.
268 * The stage consists of an ISP binary or firmware and input and
274 struct ia_css_pipeline_stage **stage) in ia_css_pipeline_create_and_add_stage() argument
294 /* Find the last stage */ in ia_css_pipeline_create_and_add_stage()
299 * stage, if no previous stage, it's an error. in ia_css_pipeline_create_and_add_stage()
313 /* Create the new stage */ in ia_css_pipeline_create_and_add_stage()
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/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dia_css_isp_params.c72 const struct ia_css_pipeline_stage *stage, in ia_css_process_aa() argument
76 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
78 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
82 … &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; in ia_css_process_aa()
92 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr() argument
99 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
102 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
109 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], in ia_css_process_anr()
113 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_anr()
127 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr2() argument
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/openbmc/qemu/include/hw/riscv/
H A Dboot_opensbi.h31 /** Representation dynamic info passed by previous booting stage */
37 /** Next booting stage address */
39 /** Next booting stage mode */
46 * It is possible that the previous booting stage uses same link
49 * stage while other HARTs are still running in the previous booting
50 * stage leading to boot-time crash. To avoid this boot-time crash,
51 * the previous booting stage can specify last HART that will jump
55 * stage can set it to -1UL which will force the FW_DYNAMIC firmware
61 /** Representation dynamic info passed by previous booting stage */
67 /** Next booting stage address */
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/openbmc/qemu/.gitlab-ci.d/
H A Dcontainer-cross.yml3 stage: containers
9 stage: containers
15 stage: containers
21 stage: containers
27 stage: containers
33 stage: containers
39 stage: containers
45 stage: containers
51 stage: containers
57 stage: containers
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/openbmc/linux/arch/riscv/errata/thead/
H A Derrata.c20 static bool errata_probe_pbmt(unsigned int stage, in errata_probe_pbmt() argument
29 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || in errata_probe_pbmt()
30 stage == RISCV_ALTERNATIVES_MODULE) in errata_probe_pbmt()
36 static bool errata_probe_cmo(unsigned int stage, in errata_probe_cmo() argument
45 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) in errata_probe_cmo()
48 if (stage == RISCV_ALTERNATIVES_BOOT) { in errata_probe_cmo()
56 static bool errata_probe_pmu(unsigned int stage, in errata_probe_pmu() argument
66 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) in errata_probe_pmu()
72 static u32 thead_errata_probe(unsigned int stage, in thead_errata_probe() argument
77 if (errata_probe_pbmt(stage, archid, impid)) in thead_errata_probe()
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/openbmc/linux/drivers/thermal/qcom/
H A Dqcom-spmi-temp-alarm.c66 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
76 unsigned int stage; member
79 /* protects .thresh, .stage and chip registers */
87 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
110 * specified over-temperature stage
112 * @stage: Over-temperature stage
116 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) in qpnp_tm_decode_temp() argument
118 if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || in qpnp_tm_decode_temp()
119 stage > STAGE_COUNT) in qpnp_tm_decode_temp()
122 return (*chip->temp_map)[chip->thresh][stage - 1]; in qpnp_tm_decode_temp()
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/openbmc/linux/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
H A Dia_css_pipeline.h25 /* Pipeline stage to be executed on SP/ISP */
31 /* SP function for SP stage */
42 /* Pipeline of n stages to be executed on SP/ISP per stage */
69 /* Stage descriptor used to create a new stage in the pipeline */
149 /* @brief Add a stage to pipeline.
152 * @param[in] stage_desc The description of the stage
153 * @param[out] stage The successor of the stage.
156 * Add a new stage to a non-NULL pipeline.
157 * The stage consists of an ISP binary or firmware and input and output
163 struct ia_css_pipeline_stage **stage);
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json39 …on is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
42 …ion is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
45 …iting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
48 …aiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
51 …ock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
54 …lock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
57 …backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
60 … backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
63 …ckend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
66 …ackend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json126 "PublicDescription": "Level 1 stage 2 TLB refill",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
144 "PublicDescription": "Page walk cache level-2 stage-1 hit",
147 "BriefDescription": "Page walk, L2 stage-1 hit"
150 "PublicDescription": "Page walk cache level-1 stage-2 hit",
153 "BriefDescription": "Page walk, L1 stage-2 hit"
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/openbmc/linux/drivers/watchdog/
H A Dkempld_wdt.c10 * First the pretimeout stage runs out before the timeout stage gets
77 struct kempld_wdt_stage stage[KEMPLD_WDT_MAX_STAGES]; member
103 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_action() argument
109 if (!stage || !stage->mask) in kempld_wdt_set_stage_action()
113 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_action()
122 kempld_write8(pld, KEMPLD_WDT_STAGE_CFG(stage->id), stage_cfg); in kempld_wdt_set_stage_action()
129 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_timeout() argument
141 if (!stage) in kempld_wdt_set_stage_timeout()
149 if (stage_timeout64 > stage->mask) in kempld_wdt_set_stage_timeout()
152 stage_timeout = stage_timeout64 & stage->mask; in kempld_wdt_set_stage_timeout()
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/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dhypercalls.c50 static int stage = TEST_STAGE_REG_IFACE; variable
104 switch (stage) { in guest_test_hvc()
108 "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%llx, stage = %u", in guest_test_hvc()
109 res.a0, hc_info->func_id, hc_info->arg1, stage); in guest_test_hvc()
113 "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%llx, stage = %u", in guest_test_hvc()
114 res.a0, hc_info->func_id, hc_info->arg1, stage); in guest_test_hvc()
117 GUEST_FAIL("Unexpected stage = %u", stage); in guest_test_hvc()
124 while (stage != TEST_STAGE_END) { in guest_code()
125 switch (stage) { in guest_code()
136 GUEST_FAIL("Unexpected stage = %u", stage); in guest_code()
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/openbmc/linux/tools/testing/selftests/kvm/x86_64/
H A Dvmx_preemption_timer_test.c163 int stage; in main() local
181 for (stage = 1;; stage++) { in main()
199 uc.args[1] == stage, "Stage %d: Unexpected register values vmexit, got %lx", in main()
200 stage, (ulong)uc.args[1]); in main()
202 * If this stage 2 then we should verify the vmx pt expiry in main()
209 if (stage == 2) { in main()
211 pr_info("Stage %d: L1 PT expiry TSC (%lu) , L1 TSC deadline (%lu)\n", in main()
212 stage, uc.args[2], uc.args[3]); in main()
214 pr_info("Stage %d: L2 PT expiry TSC (%lu) , L2 TSC deadline (%lu)\n", in main()
215 stage, uc.args[4], uc.args[5]); in main()
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H A Dset_boot_cpu_id.c48 int stage; in run_vcpu() local
50 for (stage = 0; stage < 2; stage++) { in run_vcpu()
57 uc.args[1] == stage + 1, in run_vcpu()
58 "Stage %d: Unexpected register values vmexit, got %lx", in run_vcpu()
59 stage + 1, (ulong)uc.args[1]); in run_vcpu()
63 TEST_ASSERT(stage == 1, in run_vcpu()
64 "Expected GUEST_DONE in stage 2, got stage %d", in run_vcpu()
65 stage); in run_vcpu()
H A Dhyperv_ipi.c92 int stage = 1, ipis_expected[2] = {0}; in sender_guest_code() local
95 GUEST_SYNC(stage++); in sender_guest_code()
109 GUEST_SYNC(stage++); in sender_guest_code()
116 GUEST_SYNC(stage++); in sender_guest_code()
129 GUEST_SYNC(stage++); in sender_guest_code()
138 GUEST_SYNC(stage++); in sender_guest_code()
151 GUEST_SYNC(stage++); in sender_guest_code()
160 GUEST_SYNC(stage++); in sender_guest_code()
174 GUEST_SYNC(stage++); in sender_guest_code()
183 GUEST_SYNC(stage++); in sender_guest_code()
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_lm.c18 /* These register are offset to mixer base + stage base */
35 * for the stage to be setup
37 * @stage: stage index to setup
39 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) in _stage_offset() argument
42 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) in _stage_offset()
43 return sblk->blendstage_base[stage - DPU_STAGE_0]; in _stage_offset()
95 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config_combined_alpha() argument
101 if (stage == DPU_STAGE_BASE) in dpu_hw_lm_setup_blend_config_combined_alpha()
104 stage_off = _stage_offset(ctx, stage); in dpu_hw_lm_setup_blend_config_combined_alpha()
114 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config() argument
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json39 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
42 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
45 …to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
48 … to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load"
51 … the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store",
54 …o the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store"
57 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
60 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
63 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
66 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
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/openbmc/linux/Documentation/leds/
H A Dleds-sc27xx.rst16 for the high stage. To be compatible with the hardware pattern
17 format, we should set brightness as 0 for rise stage, fall
18 stage and low stage.
20 - Min stage duration: 125 ms
21 - Max stage duration: 31875 ms
23 Since the stage duration step is 125 ms, the duration should be
/openbmc/linux/tools/testing/selftests/tc-testing/
H A DTdcPlugin.py43 def adjust_command(self, stage, command): argument
46 print(' -- {}.adjust_command {}'.format(self.sub_class, stage))
48 # if stage == 'pre':
50 # elif stage == 'setup':
52 # elif stage == 'execute':
54 # elif stage == 'verify':
56 # elif stage == 'teardown':
58 # elif stage == 'post':
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/sblim-sfcb/sblim-sfcb/
H A Dsblim-sfcb-1.4.5-service.patch20 …test -d $(DESTDIR)$(sfcbstatedir)/stage/mofs/root/interop || $(mkdir_p) $(DESTDIR)$(sfcbstatedir)/…
21 test -d $(DESTDIR)$(sfcbstatedir)/stage/regs || $(mkdir_p) $(DESTDIR)$(sfcbstatedir)/stage/regs
24 rm -f $(DESTDIR)$(sfcbstatedir)/stage/default.reg
25 rm -f $(DESTDIR)$(sfcbstatedir)/stage/mofs/root/interop/10_interop.mof
27 @INDICATIONS_TRUE@ rm -f $(DESTDIR)$(sfcbstatedir)/stage/mofs/root/interop/20_indication.mof
28 @INDICATIONS_TRUE@ rm -f $(DESTDIR)$(sfcbstatedir)/stage/mofs/indication.mof
/openbmc/linux/tools/testing/selftests/kvm/s390x/
H A Dtprot.c63 enum stage { enum
73 enum stage stage; member
139 static enum stage perform_next_stage(int *i, bool mapped_0) in perform_next_stage()
141 enum stage stage = tests[*i].stage; in perform_next_stage() local
145 for (; tests[*i].stage == stage; (*i)++) { in perform_next_stage()
163 return stage; in perform_next_stage()
185 #define HOST_SYNC_NO_TAP(vcpup, stage) \ argument
189 int __stage = (stage); \
199 #define HOST_SYNC(vcpu, stage) \ argument
201 HOST_SYNC_NO_TAP(vcpu, stage); \
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/openbmc/qemu/hw/arm/
H A Dtrace-events8 smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_…
9 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, ui…
10 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64…
11 …tw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iov…
41 …va, uint64_t translated, int perm, int stage) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64"…
50 …es, uint8_t ttl, bool leaf, int stage) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx6…
58 …t8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pa…
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mmio.c22 /* CP execution stage */
47 * execution stage into mmio area
51 /* check if exec stage has one of the valid values */
52 static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) in ipc_mmio_is_valid_exec_stage() argument
54 switch (stage) { in ipc_mmio_is_valid_exec_stage()
87 enum ipc_mem_exec_stage stage; in ipc_mmio_init() local
98 /* Check for a valid execution stage to make sure that the boot code in ipc_mmio_init()
102 stage = ipc_mmio_get_exec_stage(ipc_mmio); in ipc_mmio_init()
103 if (ipc_mmio_is_valid_exec_stage(stage)) in ipc_mmio_init()
110 dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); in ipc_mmio_init()
/openbmc/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_api.h17 #define VCAP_CID_INGRESS_L0 1000000 /* Ingress Stage 1 Lookup 0 */
18 #define VCAP_CID_INGRESS_L1 1100000 /* Ingress Stage 1 Lookup 1 */
19 #define VCAP_CID_INGRESS_L2 1200000 /* Ingress Stage 1 Lookup 2 */
20 #define VCAP_CID_INGRESS_L3 1300000 /* Ingress Stage 1 Lookup 3 */
21 #define VCAP_CID_INGRESS_L4 1400000 /* Ingress Stage 1 Lookup 4 */
22 #define VCAP_CID_INGRESS_L5 1500000 /* Ingress Stage 1 Lookup 5 */
24 #define VCAP_CID_PREROUTING_IPV6 3000000 /* Prerouting Stage */
25 #define VCAP_CID_PREROUTING 6000000 /* Prerouting Stage */
27 #define VCAP_CID_INGRESS_STAGE2_L0 8000000 /* Ingress Stage 2 Lookup 0 */
28 #define VCAP_CID_INGRESS_STAGE2_L1 8100000 /* Ingress Stage 2 Lookup 1 */
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/openbmc/linux/tools/testing/selftests/tc-testing/plugin-lib/
H A DnsPlugin.py45 def adjust_command(self, stage, command): argument
46 super().adjust_command(stage, command)
61 if stage == 'setup' or stage == 'execute' or stage == 'verify' or stage == 'teardown':
63 …print('adjust_command: stage is {}; inserting netns stuff in command [{}] list [{}]'.format(stage…
121 def _exec_cmd(self, stage, command): argument
129 self.adjust_command(stage, command)
/openbmc/linux/arch/arm64/kvm/hyp/vhe/
H A Dtlb.c29 * we cannot trust stage-1 to be in a correct state at that in __tlb_switch_to_guest()
94 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa()
95 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa()
101 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
103 * complete (S1 + S2) walk based on the old Stage-2 mapping if in __kvm_tlb_flush_vmid_ipa()
104 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
126 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa_nsh()
127 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa_nsh()
133 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
135 * complete (S1 + S2) walk based on the old Stage-2 mapping if in __kvm_tlb_flush_vmid_ipa_nsh()
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