/openbmc/u-boot/arch/arm/dts/ |
H A D | at91sam9g20.dtsi | 2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC 4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 24 compatible = "mmio-sram"; 31 compatible = "atmel,at91sam9g20-i2c"; 34 ssc0: ssc@fffbc000 { 35 compatible = "atmel,at91sam9rl-ssc"; 39 atmel,adc-startup-time = <40>; 44 atmel,clk-input-range = <2000000 32000000>; 45 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, 56 compatible = "atmel,at91sam9g20-clk-pllb"; [all …]
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H A D | at91sam9261.dtsi | 2 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC 4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com> 10 #include <dt-bindings/pinctrl/at91.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/clock/at91.h> 18 interrupt-parent = <&aic>; 38 compatible = "arm,arm926ej-s"; 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; [all …]
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H A D | at91sam9263.dtsi | 2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC 4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 10 #include <dt-bindings/pinctrl/at91.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/clock/at91.h> 18 interrupt-parent = <&aic>; 40 compatible = "arm,arm926ej-s"; 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; [all …]
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H A D | sama5d3.dtsi | 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 12 #include <dt-bindings/dma/at91.h> 13 #include <dt-bindings/pinctrl/at91.h> 14 #include <dt-bindings/interrupt-controller/irq.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/clock/at91.h> 21 interrupt-parent = <&aic>; 44 #address-cells = <1>; 45 #size-cells = <0>; 48 compatible = "arm,cortex-a5"; [all …]
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H A D | at91sam9rl.dtsi | 2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC 4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> 10 #include <dt-bindings/pinctrl/at91.h> 11 #include <dt-bindings/clock/at91.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/pwm/pwm.h> 19 interrupt-parent = <&aic>; 42 compatible = "arm,arm926ej-s"; 53 compatible = "fixed-clock"; [all …]
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H A D | exynos5420-peach-pit.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * SAMSUNG/GOOGLE Peach-Pit board device tree source 9 /dts-v1/; 11 #include <dt-bindings/clock/maxim,max77802.h> 12 #include <dt-bindings/regulator/maxim,max77802.h> 17 compatible = "google,pit-rev#", "google,pit", 21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; 22 hwid = "PIT TEST A-A 7848"; 23 lazy-init = <1>; 34 compatible = "pwm-backlight"; [all …]
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H A D | at91sam9g45.dtsi | 2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC 13 #include <dt-bindings/dma/at91.h> 14 #include <dt-bindings/pinctrl/at91.h> 15 #include <dt-bindings/interrupt-controller/irq.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/clock/at91.h> 22 interrupt-parent = <&aic>; 45 compatible = "arm,arm926ej-s"; 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; [all …]
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H A D | exynos5250-spring.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/input/input.h> 48 samsung,bl1-offset = <0x1400>; 49 samsung,bl2-offset = <0x3400>; 50 u-boot-memory = "/memory"; 51 u-boot-offset = <0x3e00000 0x100000>; 56 #address-cells = <1>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car generation 3 USB 3.0 PHY 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 - enum: 16 - renesas,r8a774a1-usb3-phy # RZ/G2M 17 - renesas,r8a774b1-usb3-phy # RZ/G2N 18 - renesas,r8a774e1-usb3-phy # RZ/G2H [all …]
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H A D | phy-miphy28lp.txt | 8 - compatible : Should be "st,miphy28lp-phy". 9 - st,syscfg : Should be a phandle of the system configuration register group 12 Required nodes : A sub-node is required for each channel the controller 13 provides. Address range information including the usual 14 'reg' and 'reg-names' properties are used inside these 19 - #phy-cells : Should be 1 (See second example) 21 - PHY_TYPE_SATA 22 - PHY_TYPE_PCI 23 - PHY_TYPE_USB3 24 - reg : Address and length of the register set for the device. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexander Stein <alexander.stein@ew.tq-group.com> 13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction 15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913 16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925 17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937 18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949 23 - ti,cdce913 [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-st-ssc4.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2008-2014 STMicroelectronics Limited 25 /* SSC registers */ 33 /* SSC Control */ 48 /* SSC Interrupt Enable */ 54 /* SSC SPI Controller */ 59 /* SSC SPI current transaction */ 74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo() 77 count = spi_st->words_remaining; in ssc_write_tx_fifo() 80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo() [all …]
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/openbmc/linux/sound/spi/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 21 This driver requires the Atmel SSC driver for sound sink, a 25 called snd-at73c213. 31 range 8000 50000
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/openbmc/linux/drivers/phy/st/ |
H A D | phy-miphy28lp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 25 #include <dt-bindings/phy/phy.h> 171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 211 bool ssc; member 238 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" }; 367 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset() 378 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset() 379 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset() 391 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration() [all …]
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/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_pch_refclk.c | 1 // SPDX-License-Identifier: MIT 19 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy() 25 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy() 111 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip() 117 mutex_unlock(&dev_priv->sb_lock); in lpt_disable_iclkip() 130 p->iclk_virtual_root_freq = 172800 * 1000; in iclkip_params_init() 131 p->iclk_pi_range = 64; in iclkip_params_init() 136 return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_iclkip_freq() 137 p->desired_divisor << p->auxdiv); in lpt_iclkip_freq() 145 * but the adjusted_mode->crtc_clock in KHz. To get the in lpt_compute_iclkip() [all …]
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/openbmc/u-boot/cmd/aspeed/ |
H A D | dptest.h | 1 /* SPDX-License-Identifier: GPL-2.0+ 64 /* Re-driver setting */ 146 #define F_EMPHASIS 0x00000002 // Emphasis : 1-0-2 147 #define F_EMPHASIS_1 0x00000004 // Emphasis 1 : 2-0-1 166 #define PRINT_DEEMP_0 printf("DP Pre - Emphasis Level 0!\n") 167 #define PRINT_DEEMP_1 printf("DP Pre - Emphasis Level 1!\n") 168 #define PRINT_DEEMP_2 printf("DP Pre - Emphasis Level 2!\n") 170 #define PRINT_EMPVAL_0 printf("DP Pre - Emphasis Level 0 !\n") 171 #define PRINT_EMPVAL_1 printf("DP Pre - Emphasis Level 1 !\n") 172 #define PRINT_EMPVAL_2 printf("DP Pre - Emphasis Level 2 !\n") [all …]
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H A D | dptest.c | 1 // SPDX-License-Identifier: GPL-2.0+ 104 if (argv[i][0] == '-') { in do_ast_dptest() 144 printf("0: Change SSC on/off\n"); in do_ast_dptest() 152 printf("6: SSC shift -80ppm\n"); in do_ast_dptest() 153 printf("7: SSC shift -120ppm\n"); in do_ast_dptest() 289 case 'd': /* Non-Transition Voltage Range Measurement - PLTPAT */ in do_ast_dptest() 293 case 'e': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ in do_ast_dptest() 297 case 'f': /* Non-Transition Voltage Range Measurement - PRBS7 */ in do_ast_dptest() 315 case 'x': /* Auto hand shaking with DPR-100 */ in do_ast_dptest() 320 printf("Non - define command!\n"); in do_ast_dptest() [all …]
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/openbmc/linux/block/ |
H A D | opal_proto.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 16 * SPC-4 section 218 /* Locking state for a locking range */ 283 * Opal SSC Documentation 337 * bits 6-7: reserved 369 * bits 1-6: reserved 380 * Enterprise SSC Feature 388 * bits 1-6: reserved 389 * bit 0: range crossing 419 * bits 3-7: reserved [all …]
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-platform-dptf | 4 Contact: linux-acpi@vger.kernel.org 6 (RO) The charger type - Traditional, Hybrid or NVDC. 11 Contact: linux-acpi@vger.kernel.org 19 Contact: linux-acpi@vger.kernel.org 27 Contact: linux-acpi@vger.kernel.org 33 - 0x00 = DC 34 - 0x01 = AC 35 - 0x02 = USB 36 - 0x03 = Wireless Charger 43 Contact: linux-acpi@vger.kernel.org [all …]
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/openbmc/linux/drivers/phy/renesas/ |
H A D | phy-rcar-gen3-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Renesas R-Car Gen3 for USB3.0 PHY driver 65 writew(val, r->base + USB30_CLKSET1); in write_clkset1_for_usb_extal() 72 switch (r->ssc_range) { in rcar_gen3_phy_usb3_enable_ssc() 83 dev_err(&r->phy->dev, "%s: unsupported range (%x)\n", __func__, in rcar_gen3_phy_usb3_enable_ssc() 84 r->ssc_range); in rcar_gen3_phy_usb3_enable_ssc() 88 writew(val, r->base + USB30_SSC_SET); in rcar_gen3_phy_usb3_enable_ssc() 94 if (r->ssc_range) in rcar_gen3_phy_usb3_select_usb_extal() 97 r->base + USB30_CLKSET0); in rcar_gen3_phy_usb3_select_usb_extal() 98 writew(PHY_ENABLE_RESET_EN, r->base + USB30_PHY_ENABLE); in rcar_gen3_phy_usb3_select_usb_extal() [all …]
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/openbmc/qemu/target/arm/ |
H A D | debug_helper.c | 6 * SPDX-License-Identifier: GPL-2.0-or-later 12 #include "cpu-features.h" 14 #include "exec/exec-all.h" 15 #include "exec/helper-proto.h" 30 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || in arm_debug_target_el() 31 env->cp15.mdcr_el2 & MDCR_TDE; in arm_debug_target_el() 76 && extract32(env->cp15.mdcr_el3, 16, 1)) { in aa64_generate_debug_exceptions() 87 return extract32(env->cp15.mdscr_el1, 13, 1) in aa64_generate_debug_exceptions() 88 && !(env->daif & PSTATE_D); in aa64_generate_debug_exceptions() 106 if (el == 0 && (env->cp15.sder & 1)) { in aa32_generate_debug_exceptions() [all …]
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/openbmc/linux/Documentation/scsi/ |
H A D | FlashPoint.rst | 1 .. SPDX-License-Identifier: GPL-2.0 17 FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux 33 Linux is a freely-distributed implementation of UNIX for Intel x86, Sun 35 machines. It supports a wide range of software, including the X Window 37 http://www.linux.org and http://www.ssc.com/. 55 and system boards. Through its wide range of RAID controllers and its 71 510/796-6100 78 BusLogic FlashPoint LT/BT-948 Upgrade Program 82 BusLogic FlashPoint LW/BT-958 Upgrade Program 99 customers to make sure the BT-946C/956C MultiMaster cards would still be [all …]
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/openbmc/linux/drivers/gpu/drm/bridge/ |
H A D | parade-ps8622.c | 1 // SPDX-License-Identifier: GPL-2.0-only 68 struct i2c_adapter *adap = client->adapter; in ps8622_set() 72 msg.addr = client->addr + page; in ps8622_set() 80 client->addr + page, reg, val, ret); in ps8622_set() 86 struct i2c_client *cl = ps8622->client; in ps8622_send_config() 137 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config() 147 /* Gitune=-37% */ in ps8622_send_config() 167 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config() 179 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config() 184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config() [all …]
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 9 #include <linux/clk-provider.h> 73 * struct tegra_clk_sync_source - external clock source from codec 75 * @hw: handle between common and hardware-specific interfaces 95 * struct tegra_clk_frac_div - fractional divider clock 97 * @hw: handle between common and hardware-specific interfaces 99 * @flags: hardware-specific flags 106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when [all …]
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/openbmc/linux/drivers/gpu/drm/msm/dsi/phy/ |
H A D | dsi_phy_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 17 * DSI PLL 14nm - clock diagram (eg: DSI0): 22 * +----+ | +----+ 23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte 24 * +----+ | +----+ 26 * | +----+ | 27 * o---| /2 |--o--|\ 28 * | +----+ | \ +----+ 29 * | | |--| n2 |-- dsi0pll [all …]
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