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/openbmc/u-boot/drivers/pch/
H A DKconfig7 northbridge / southbridge architecture that was previously used. The
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Chassis/Control/
H A DNMISource.interface.yaml41 Via southbridge NMI.
/openbmc/phosphor-dbus-interfaces/yaml/com/intel/Control/
H A DNMISource.interface.yaml43 Via southbridge NMI.
/openbmc/qemu/hw/i2c/
H A Dsmbus_ich9.c30 #include "hw/southbridge/ich9.h"
136 * Reason: part of ICH9 southbridge, needs to be wired up by in ich9_smb_class_init()
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dme.h3 * From Coreboot src/southbridge/intel/bd82x6x/me.h
H A Dpch.h5 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
/openbmc/qemu/hw/acpi/
H A Dich9_timer.c13 #include "hw/southbridge/ich9.h"
H A Dich9_tco.c12 #include "hw/southbridge/ich9.h"
H A Dich9.c40 #include "hw/southbridge/ich9.h"
H A Dpiix4.c643 * Reason: part of PIIX4 southbridge, needs to be wired up, in piix4_pm_class_init()
/openbmc/qemu/tests/functional/
H A Dtest_mips64el_fuloong2e.py46 # (enough to test the fuloong2e southbridge, accessing its ISA bus)
/openbmc/u-boot/board/freescale/common/
H A Dcds_via.c29 * southbridge to be accessed. in mpc85xx_config_via()
/openbmc/qemu/hw/pci-bridge/
H A Di82801b11.c48 #include "hw/southbridge/ich9.h"
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dearly_me.c3 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
H A Dlpc.c3 * From coreboot southbridge/intel/bd82x6x/lpc.c
483 /* Setting up Southbridge. In the northbridge code. */ in bd82x6x_lpc_early_init()
484 debug("Setting up static southbridge registers\n"); in bd82x6x_lpc_early_init()
/openbmc/qemu/hw/isa/
H A Dpiix.c30 #include "hw/southbridge/piix.h"
433 * Reason: part of PIIX southbridge, needs to be wired up by e.g. in pci_piix_class_init()
H A Dlpc_ich9.c43 #include "hw/southbridge/ich9.h"
897 * Reason: part of ICH9 southbridge, needs to be wired up by in ich9_lpc_class_init()
H A Dvt82c686.c850 /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ in vt82c686b_class_init()
915 /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ in vt8231_class_init()
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
/openbmc/u-boot/arch/x86/lib/
H A Dmrccache.c3 * From coreboot src/southbridge/intel/bd82x6x/mrccache.c
/openbmc/u-boot/arch/x86/include/asm/
H A Dme_common.h3 * From Coreboot src/southbridge/intel/bd82x6x/me.h
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dme_status.c3 * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
/openbmc/qemu/hw/ide/
H A Dvia.c255 /* Reason: only works as function of VIA southbridge */ in via_ide_class_init()
/openbmc/qemu/tests/qtest/
H A Dtco-test.c17 #include "hw/southbridge/ich9.h"
/openbmc/qemu/hw/i386/
H A Dpc_q35.c54 #include "hw/southbridge/ich9.h"

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