| /openbmc/linux/drivers/clk/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
22 Choose Y here only if you build for this SoC.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
29 Choose Y here only if you build for this SoC.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
[all …]
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| /openbmc/linux/drivers/soc/renesas/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
67 bool "ARM32 Platform support for R-Car E2"
73 bool "ARM32 Platform support for R-Car H1"
82 bool "ARM32 Platform support for R-Car H2"
90 bool "ARM32 Platform support for R-Car M1A"
95 bool "ARM32 Platform support for R-Car M2-N"
102 bool "ARM32 Platform support for R-Car M2-W"
109 bool "ARM32 Platform support for R-Car V2H"
115 bool "ARM32 Platform support for R-Mobile A1"
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| /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
38 If you have a controller with this interface, say Y or M here.
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
65 Support for Adaptrum Anarion GMAC Ethernet controller.
67 This selects the Anarion SoC glue layer support for the stmmac driver.
75 Support for ethernet controller on Ingenic SoCs.
79 MAC ethernet controller.
89 This selects the IPQ806x SoC glue layer support for the stmmac
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| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
36 Say Y here if you want to enable PCI controller support on Amlogic
37 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
38 and therefore the driver re-uses the DesignWare core functions to
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| /openbmc/linux/drivers/clk/meson/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
52 bool "Meson8 SoC Clock controller support"
62 Support for the clock controller on AmLogic S802 (Meson8),
67 tristate "GXBB and GXL SoC clock controllers support"
79 Support for the clock controller on AmLogic S905 devices, aka gxbb.
83 tristate "AXG SoC clock controllers support"
94 Support for the clock controller on AmLogic A113D devices, aka axg.
98 tristate "Meson AXG Audio Clock Controller Driver"
106 Support for the audio clock controller on AmLogic A113D devices,
110 tristate "Amlogic A1 SoC PLL controller support"
[all …]
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| /openbmc/linux/drivers/clk/starfive/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Say yes here to support the clock controller on the StarFive JH7100
13 SoC.
22 SoC.
29 Say yes here to support the PLL clock controller on the
30 StarFive JH7110 SoC.
41 Say yes here to support the system clock controller on the
42 StarFive JH7110 SoC.
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/soc/litex/ |
| H A D | litex,soc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: LiteX SoC Controller driver
11 This is the SoC Controller driver for the LiteX SoC Builder.
17 - Karol Gugala <kgugala@antmicro.com>
18 - Mateusz Holenko <mholenko@antmicro.com>
22 const: litex,soc-controller
28 - compatible
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
18 tristate "Sunplus SP7021 MMC Controller"
37 bool "Qualcomm Data Mover for SD Card Controller"
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
48 bool "STMicroelectronics STM32 SDMMC Controller"
52 This selects the STMicroelectronics STM32 SDMMC host controller.
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
[all …]
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| /openbmc/linux/drivers/pinctrl/spear/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
26 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
32 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
38 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
44 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
50 bool "SPEAr SoC PLGPIO Controller"
54 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
28 functionality as may be required for the SoC. This hierarchy also describes the
[all …]
|
| /openbmc/linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
39 bool "BCM6345 Reset Controller"
43 This enables the reset controller driver for BCM6345 SoCs.
50 This enables the reset controller driver for Marvell Berlin SoCs.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
|
| H A D | brcm,iproc-gpio.txt | 1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
|
| /openbmc/linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
14 controller is part of the South Bridge of the Marvel Armada
15 3700 SoC.
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
30 This MSI driver supports Altera MSI to GIC controller IP.
38 tristate "Apple PCIe controller"
[all …]
|
| /openbmc/linux/drivers/gpu/drm/sun4i/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 Choose this option if you have an Allwinner SoC with a
14 sun4i-drm.
19 tristate "Allwinner A10/A10s/A20/A31 HDMI Controller Support"
24 SoC with an HDMI controller.
33 SoC with an HDMI controller and want to use CEC.
40 Choose this option if you have an Allwinner SoC with the
43 selected the module will be called sun4i-backend.
46 tristate "Allwinner A31/A64 MIPI-DSI Controller Support"
53 Choose this option if you want have an Allwinner SoC with
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-mpc8xxx.txt | 1 * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
4 - compatible : Should be "fsl,<soc>-gpio"
5 The following <soc>s are known to be supported:
8 - reg : Address and length of the register set for the device
9 - interrupts : Should be the port interrupt shared by all 32 pins.
10 - #gpio-cells : Should be two. The first cell is the pin number and
16 - little-endian : GPIO registers are used as little endian. If not
19 Example of gpio-controller node for a mpc5125 SoC:
22 compatible = "fsl,mpc5125-gpio";
23 #gpio-cells = <2>;
[all …]
|
| H A D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
[all …]
|
| /openbmc/linux/drivers/pinctrl/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
53 tristate "Apple SoC GPIO pin controller driver"
62 This is the driver for the GPIO controller found on Apple ARM SoCs,
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
86 functionality. This driver supports the pinmux, push-pull and
114 controller available on sama5d2 SoC.
117 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
[all …]
|
| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 1 SoC overview
13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
19 The LS1043A SoC includes the following function and features:
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
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|
| /openbmc/u-boot/drivers/mmc/ |
| H A D | Kconfig | 1 menu "MMC Host controller Support"
12 also to your specific host controller driver.
31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
161 you are reading this help text, you most likely have no idea :-)
193 This selects support for Samsung Exynos SoC specific extensions to the
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
15 domains of the SoC.
20 - const: canaan,k210-sysctl
21 - const: syscon
[all …]
|
| /openbmc/linux/drivers/usb/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # USB Host Controller Drivers
5 comment "USB Host Controller Drivers"
11 The Cypress C67x00 (EZ-Host/EZ-OTG) chips are dual-role
14 Enable this option to support this chip in host controller mode.
24 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
25 "SuperSpeed" host controller hardware.
28 module will be called xhci-hcd.
47 tristate "Support for additional Renesas xHCI controller with firmware"
49 Say 'Y' to enable the support for the Renesas xHCI controller with
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,s3c64xx-clock.txt | 1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
20 on a particular S3C64xx SoC and this is specified where applicable.
23 dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
[all …]
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
19 tristate "Denali NAND controller on Intel Moorestown"
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
32 controller as a DT device.
35 tristate "Amstrad E3 NAND controller"
42 tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller"
69 This enables the driver for the NAND flash controller on the
70 AMD/Alchemy 1550 SOC.
[all …]
|