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/openbmc/linux/mm/
H A Dpage_io.c259 struct swap_iocb *sio = container_of(iocb, struct swap_iocb, iocb); in sio_write_complete() local
260 struct page *page = sio->bvec[0].bv_page; in sio_write_complete()
263 if (ret != sio->len) { in sio_write_complete()
276 for (p = 0; p < sio->pages; p++) { in sio_write_complete()
277 page = sio->bvec[p].bv_page; in sio_write_complete()
282 for (p = 0; p < sio->pages; p++) in sio_write_complete()
283 count_swpout_vm_event(page_folio(sio->bvec[p].bv_page)); in sio_write_complete()
286 for (p = 0; p < sio->pages; p++) in sio_write_complete()
287 end_page_writeback(sio->bvec[p].bv_page); in sio_write_complete()
289 mempool_free(sio, sio_pool); in sio_write_complete()
[all …]
H A Dswap.h18 void swap_write_unplug(struct swap_iocb *sio);
70 static inline void swap_write_unplug(struct swap_iocb *sio) in swap_write_unplug() argument
/openbmc/linux/drivers/gpio/
H A Dgpio-f7188x.c93 struct f7188x_sio *sio; member
292 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get_direction() local
295 err = superio_enter(sio->addr); in f7188x_gpio_get_direction()
298 superio_select(sio->addr, sio->device); in f7188x_gpio_get_direction()
300 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
302 superio_exit(sio->addr); in f7188x_gpio_get_direction()
304 if (f7188x_gpio_dir_invert(sio->type)) in f7188x_gpio_get_direction()
317 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_direction_in() local
320 err = superio_enter(sio->addr); in f7188x_gpio_direction_in()
323 superio_select(sio->addr, sio->device); in f7188x_gpio_direction_in()
[all …]
/openbmc/qemu/hw/isa/
H A Disa-superio.c30 ISASuperIODevice *sio = ISA_SUPERIO(dev); in isa_superio_realize() local
31 ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio); in isa_superio_realize()
42 if (i >= ARRAY_SIZE(sio->parallel)) { in isa_superio_realize()
44 k->parallel.count - ARRAY_SIZE(sio->parallel)); in isa_superio_realize()
47 if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) { in isa_superio_realize()
61 k->parallel.get_iobase(sio, i)); in isa_superio_realize()
64 qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i)); in isa_superio_realize()
69 sio->parallel[i] = isa; in isa_superio_realize()
72 k->parallel.get_iobase(sio, i) : -1, in isa_superio_realize()
74 k->parallel.get_irq(sio, i) : -1); in isa_superio_realize()
[all …]
H A Dpc87312.c66 static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index) in is_parallel_enabled() argument
68 PC87312State *s = PC87312(sio); in is_parallel_enabled()
74 static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index) in get_parallel_iobase() argument
76 PC87312State *s = PC87312(sio); in get_parallel_iobase()
82 static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index) in get_parallel_irq() argument
84 PC87312State *s = PC87312(sio); in get_parallel_irq()
102 static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i) in get_uart_iobase() argument
104 PC87312State *s = PC87312(sio); in get_uart_iobase()
116 static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i) in get_uart_irq() argument
118 PC87312State *s = PC87312(sio); in get_uart_irq()
[all …]
H A Dsmc37c669-superio.c17 static uint16_t get_serial_iobase(ISASuperIODevice *sio, uint8_t index) in get_serial_iobase() argument
22 static unsigned int get_serial_irq(ISASuperIODevice *sio, uint8_t index) in get_serial_irq() argument
29 static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index) in get_parallel_iobase() argument
34 static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index) in get_parallel_irq() argument
39 static unsigned int get_parallel_dma(ISASuperIODevice *sio, uint8_t index) in get_parallel_dma() argument
46 static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index) in get_fdc_iobase() argument
51 static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index) in get_fdc_irq() argument
56 static unsigned int get_fdc_dma(ISASuperIODevice *sio, uint8_t index) in get_fdc_dma() argument
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6-pins.h10 #define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ argument
11 prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
15 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
16 MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
19 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
20 MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
25 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
26 MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
31 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
32 MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
/openbmc/linux/drivers/parisc/
H A Dsuperio.c151 struct superio_device *sio = &sio_dev; in superio_init() local
152 struct pci_dev *pdev = sio->lio_pdev; in superio_init()
156 if (sio->suckyio_irq_enabled) in superio_init()
160 BUG_ON(!sio->usb_pdev); in superio_init()
163 pdev->irq = sio->usb_pdev->irq; in superio_init()
166 sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev); in superio_init()
171 pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base); in superio_init()
172 sio->sp1_base &= ~1; in superio_init()
173 printk(KERN_INFO PFX "Serial port 1 at 0x%x\n", sio->sp1_base); in superio_init()
175 pci_read_config_dword (pdev, SIO_SP2BAR, &sio->sp2_base); in superio_init()
[all …]
/openbmc/qemu/include/hw/isa/
H A Dsuperio.h39 bool (*is_enabled)(ISASuperIODevice *sio, uint8_t index);
40 uint16_t (*get_iobase)(ISASuperIODevice *sio, uint8_t index);
41 unsigned int (*get_irq)(ISASuperIODevice *sio, uint8_t index);
42 unsigned int (*get_dma)(ISASuperIODevice *sio, uint8_t index);
/openbmc/linux/drivers/net/ethernet/ti/
H A Dtlan.c2234 u8 sio; in tlan_finish_reset() local
2302 sio = tlan_dio_read8(dev->base_addr, TLAN_NET_SIO); in tlan_finish_reset()
2303 sio |= TLAN_NET_SIO_MINTEN; in tlan_finish_reset()
2304 tlan_dio_write8(dev->base_addr, TLAN_NET_SIO, sio); in tlan_finish_reset()
2828 * the TLAN SIO register.
2836 u16 sio, tmp; in __tlan_mii_read_reg() local
2846 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; in __tlan_mii_read_reg()
2850 minten = tlan_get_bit(TLAN_NET_SIO_MINTEN, sio); in __tlan_mii_read_reg()
2852 tlan_clear_bit(TLAN_NET_SIO_MINTEN, sio); in __tlan_mii_read_reg()
2860 tlan_clear_bit(TLAN_NET_SIO_MTXEN, sio); /* change direction */ in __tlan_mii_read_reg()
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsys_sio.c9 * Code for all boards that route the PCI interrupts through the SIO
95 orig_route_tab, alpha_mv.sys.sio.route_tab); in sio_pci_route()
103 alpha_mv.sys.sio.route_tab); in sio_pci_route()
189 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ in noname_map_irq()
200 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); in noname_map_irq()
217 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ in p2k_map_irq()
226 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); in p2k_map_irq()
355 .sys = { .sio = {
385 .sys = { .sio = {
414 .sys = { .sio = {
[all …]
H A Dsys_cabriolet.c174 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
184 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ in eb66p_map_irq()
204 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
215 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ in cabriolet_map_irq()
251 * PCI slots, the SIO, PCI/IDE, and USB.
271 * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
299 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ in alphapc164_map_irq()
/openbmc/u-boot/drivers/pinctrl/mscc/
H A Dpinctrl-luton.c42 [FUNC_SIO] = "sio",
53 MSCC_P(0, SIO, NONE, NONE);
54 MSCC_P(1, SIO, NONE, NONE);
55 MSCC_P(2, SIO, NONE, NONE);
56 MSCC_P(3, SIO, NONE, NONE);
H A Dpinctrl-serval.c85 [FUNC_SIO] = "sio",
96 MSCC_P(0, SIO, NONE, NONE);
97 MSCC_P(1, SIO, NONE, NONE);
98 MSCC_P(2, SIO, NONE, NONE);
99 MSCC_P(3, SIO, NONE, NONE);
H A Dpinctrl-servalt.c112 [FUNC_SIO] = "sio",
122 MSCC_P(0, SIO, NONE, NONE);
123 MSCC_P(1, SIO, NONE, NONE);
124 MSCC_P(2, SIO, NONE, NONE);
125 MSCC_P(3, SIO, NONE, NONE);
/openbmc/linux/Documentation/hwmon/
H A Dsmsc47b397.rst35 Methods for detecting the HP SIO and reading the thermal data on a dc7100
38 The thermal information on the dc7100 is contained in the SIO Hardware Monitor
90 The SIO counts the number of 90kHz (11.111us) pulses per revolution.
102 Obtaining the SIO version.
146 The following is an example of how to read the SIO Device ID located at 0x20:
164 The registers of interest for identifying the SIO on the dc7100 are Device ID
/openbmc/linux/drivers/md/
H A Ddm-io.c421 struct sync_io *sio = context; in sync_io_complete() local
423 sio->error_bits = error; in sync_io_complete()
424 complete(&sio->wait); in sync_io_complete()
432 struct sync_io sio; in sync_io() local
439 init_completion(&sio.wait); in sync_io()
446 io->context = &sio; in sync_io()
453 wait_for_completion_io(&sio.wait); in sync_io()
456 *error_bits = sio.error_bits; in sync_io()
458 return sio.error_bits ? -EIO : 0; in sync_io()
/openbmc/linux/drivers/spi/
H A Dspi-lm70llp.c64 #define SIO 0x10 macro
153 * Why do we return 0 when the SIO line is high and vice-versa?
155 * is wired in just such a way : when the lm70's SIO goes high, a transistor
162 return ((SIO == (parport_read_status(pp->port) & SIO)) ? 0 : 1); in getmiso()
/openbmc/u-boot/include/
H A Dns87308.h101 #define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
102 #define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
103 #define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
104 #define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
/openbmc/u-boot/drivers/misc/
H A Dali512x.c238 * Reigster 3 in the SIO is used to select the index and data
241 * function SIO 8.
243 * SIO reigster 3 (CIO Address Selection) bit definitions:
258 * SIO registers, each register have the same format:
267 * SIO REG
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pow.h1571 ptr.sio.mem_region = CVMX_IO_SEG; in cvmx_pow_tag_sw_nocheck()
1572 ptr.sio.is_io = 1; in cvmx_pow_tag_sw_nocheck()
1573 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; in cvmx_pow_tag_sw_nocheck()
1683 ptr.sio.mem_region = CVMX_IO_SEG; in cvmx_pow_tag_sw_full_nocheck()
1684 ptr.sio.is_io = 1; in cvmx_pow_tag_sw_full_nocheck()
1685 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; in cvmx_pow_tag_sw_full_nocheck()
1686 ptr.sio.offset = CAST64(wqp); in cvmx_pow_tag_sw_full_nocheck()
1760 ptr.sio.mem_region = CVMX_IO_SEG; in cvmx_pow_tag_sw_null_nocheck()
1761 ptr.sio.is_io = 1; in cvmx_pow_tag_sw_null_nocheck()
1762 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; in cvmx_pow_tag_sw_null_nocheck()
[all …]
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c49 /* Through tasklet to do sio write. */
192 * ipc_imem_sys_port_close - Release a sio link to CP.
205 /* If current phase is IPC_P_OFF or SIO ID is -ve then in ipc_imem_sys_port_close()
345 /* Open a SIO link to CP and return the channel instance */
393 dev_err(ipc_imem->dev, "SIO open refused, phase %d", phase); in ipc_imem_sys_devlink_open()
399 /* Release a SIO channel link to CP. */
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml13 By using a serial interface, the SIO controller significantly extend
15 pins on the device. The primary purpose of the SIO controllers is to
/openbmc/linux/drivers/hwmon/
H A Dw83627hf.c100 superio_outb(struct w83627hf_sio_data *sio, int reg, int val) in superio_outb() argument
102 outb(reg, sio->sioaddr); in superio_outb()
103 outb(val, sio->sioaddr + 1); in superio_outb()
107 superio_inb(struct w83627hf_sio_data *sio, int reg) in superio_inb() argument
109 outb(reg, sio->sioaddr); in superio_inb()
110 return inb(sio->sioaddr + 1); in superio_inb()
114 superio_select(struct w83627hf_sio_data *sio, int ld) in superio_select() argument
116 outb(DEV, sio->sioaddr); in superio_select()
117 outb(ld, sio->sioaddr + 1); in superio_select()
121 superio_enter(struct w83627hf_sio_data *sio) in superio_enter() argument
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Ddma.h81 These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
86 hardware SIO limitation, is 64MB.
91 due to an hardware SIO limitation, is 16MB.
96 due to an hardware SIO chip limitation, is 2GB.

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