| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | Kconfig | 15 bool "Enable multiple CPUs to enter into U-Boot"
21 CPUECTLR_EL1.SMPEN bit before U-Boot.
36 bool "Support spin-table enable method"
39 Say Y here to support "spin-table" enable method for booting Linux.
42 - Specify enable-method = "spin-table" in each CPU node in the
44 - Bring secondary CPUs into U-Boot proper in a board specific
49 U-Boot automatically does:
50 - Set "cpu-release-addr" property of each CPU node
52 - Reserve the code for the spin-table and the release address
55 menu "ARMv8 secure monitor firmware"
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| H A D | exception_level.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Switch to non-secure mode
16 * entry_non_secure() - entry point when switching to non-secure mode
18 * When switching to non-secure mode switch_to_non_secure_mode() calls this
27 debug("Reached non-secure mode\n"); in entry_non_secure()
34 * switch_to_non_secure_mode() - switch to non-secure mode
36 * Exception level EL3 is meant to be used by the secure monitor only (ARM
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| /openbmc/linux/arch/arm/mach-bcm/ |
| H A D | bcm_kona_smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
52 pr_info("Kona Secure API initialized\n"); in bcm_kona_smc_init()
60 * Only core 0 can run the secure monitor code. If an "smc" request
67 * cache and interrupt handling while the secure monitor executes.
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
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| /openbmc/linux/drivers/firmware/meson/ |
| H A D | meson_sm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Secure Monitor driver
9 #define pr_fmt(fmt) "meson-sm: " fmt
11 #include <linux/arm-smccc.h>
62 const struct meson_sm_cmd *cmd = chip->cmd; in meson_sm_get_cmd()
64 while (cmd->smc_id && cmd->index != cmd_index) in meson_sm_get_cmd()
67 return cmd->smc_id; in meson_sm_get_cmd()
91 * meson_sm_call - generic SMC32 call to the secure-monitor
93 * @fw: Pointer to secure-monitor firmware
109 if (!fw->chip) in meson_sm_call()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Amlogic Secure Monitor driver
6 tristate "Amlogic Secure Monitor driver"
11 Say y here to enable the Amlogic secure monitor driver
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| /openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | amlogic,meson-gxbb-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: nvmem.yaml#
18 - const: amlogic,meson-gxbb-efuse
19 - items:
20 - const: amlogic,meson-gx-efuse
21 - const: amlogic,meson-gxbb-efuse
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| /openbmc/linux/include/linux/firmware/intel/ |
| H A D | stratix10-smc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
9 #include <linux/arm-smccc.h>
13 * This file defines the Secure Monitor Call (SMC) message protocol used for
14 * service layer driver in normal world (EL1) to communicate with secure
15 * monitor software in Secure Monitor Exception Level 3 (EL3).
17 * This file is shared with secure firmware (FW) which is out of kernel tree.
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
21 * value. The operation of the secure monitor is determined by the parameter
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| /openbmc/linux/Documentation/devicetree/bindings/firmware/ |
| H A D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
10 communication with SDM, only the secure world of software (EL3, Exception
18 driver also manages secure monitor call (SMC) to communicate with secure monitor
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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| H A D | amlogic,meson-gxbb-sm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Secure Monitor (SM)
10 In the Amlogic SoCs the Secure Monitor code is used to provide access to the
14 - Neil Armstrong <neil.armstrong@linaro.org>
19 - const: amlogic,meson-gxbb-sm
20 - items:
21 - const: amlogic,meson-gx-sm
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| H A D | brcm,kona-smc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family Secure Monitor bounce buffer
10 A bounce buffer used for non-secure to secure communications.
13 - Florian Fainelli <f.fainelli@gmail.com>
18 - enum:
19 - brcm,bcm11351-smc
20 - brcm,bcm21664-smc
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| /openbmc/linux/drivers/firmware/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
19 provides a mechanism for inter-processor communication between SCP
71 bool "Add firmware-provided memory map to sysfs" if EXPERT
74 Add the firmware-provided (unmodified) memory map to /sys/firmware/memmap.
78 See also Documentation/ABI/testing/sysfs-firmware-memmap.
111 DMI-based module auto-loading.
183 and manages secure monitor call to communicate with secure monitor
184 software at secure monitor exception level.
223 warm-restart enter a special debug mode that allows the user to
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| /openbmc/u-boot/board/freescale/common/ |
| H A D | Kconfig | 19 This option enables two commands used for secure booting:
21 esbc_validate - validate signature using RSA verification
22 esbc_halt - put the core in spin loop (Secure Boot Only)
26 bool "Enable the LTC3882 voltage monitor read"
29 This option enables LTC3882 voltage monitor read
34 bool "Enable the LTC3882 voltage monitor set"
37 This option enables LTC3882 voltage monitor set
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap-secure.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * omap-secure.h: OMAP Secure infrastructure header.
15 /* Monitor error code */
23 /* Secure HAL API flags */
30 /* Maximum Secure memory storage size */
35 /* Secure low power HAL API index */
41 /* Secure Monitor mode APIs */
52 /* Secure PPA(Primary Protected Application) APIs */
60 /* Secure RX-51 PPA (Primary Protected Application) APIs */
|
| H A D | omap-smc.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * OMAP34xx and OMAP44xx secure APIs file.
15 * This is common routine to manage secure monitor API
16 * used to modify the PL310 secure registers.
18 * the monitor API number. It uses few CPU registers
23 .arch armv7-a
26 stmfd sp!, {r2-r12, lr}
31 ldmfd sp!, {r2-r12, pc}
36 * Low level common routine for secure HAL and PPA APIs.
43 stmfd sp!, {r4-r12, lr}
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| /openbmc/linux/Documentation/devicetree/bindings/power/ |
| H A D | amlogic,meson-sec-pwrc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 ---
6 $id: http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Amlogic Meson Secure Power Domains
12 - Jianxin Pan <jianxin.pan@amlogic.com>
15 Secure Power Domains used in Meson A1/C1/S4 & C3 SoCs, and should be the child node
16 of secure-monitor.
21 - amlogic,meson-a1-pwrc
22 - amlogic,meson-s4-pwrc
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| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | nonsec_virt.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
12 #include <asm/proc-armv/ptrace.h>
20 /* the vector table for secure state and HYP mode */
38 * secure monitor handler
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
47 ldr r5, =_psci_vectors @ Switch to the next monitor
51 @ Obtain a secure stack
77 @ FIQ preserved for secure mode
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| H A D | virt-dt.c | 2 * Copyright (C) 2013 - ARM Ltd
42 debug("Secure monitor larger than RAM bank!?\n"); in armv7_apply_memory_carveout()
43 return -EINVAL; in armv7_apply_memory_carveout()
45 *size -= CONFIG_ARMV7_SECURE_RESERVE_SIZE; in armv7_apply_memory_carveout()
50 debug("Secure monitor not located at beginning or end of RAM bank\n"); in armv7_apply_memory_carveout()
51 return -EINVAL; in armv7_apply_memory_carveout()
64 /* secure code lives in RAM, keep it alive */ in psci_update_dt()
66 __secure_end - __secure_start); in psci_update_dt()
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| /openbmc/openbmc/meta-ibm/recipes-phosphor/state/ |
| H A D | phosphor-state-manager_%.bbappend | 2 PACKAGECONFIG:append:witherspoon = " no-warm-reboot"
5 PACKAGECONFIG:append:p10bmc = " no-force-warm-reboot"
8 PACKAGECONFIG:append = " only-run-apr-on-power-loss"
11 PACKAGECONFIG:append = " only-allow-boot-when-bmc-ready"
13 # The scheduled-host-transition package provides support to
16 RRECOMMENDS:${PN}-host:append = " ${PN}-scheduled-host-transition"
21 RRECOMMENDS:${PN}-host:append = " ${PN}-hypervisor"
23 # IBM p10 machines want the optional secure-check
26 RRECOMMENDS:${PN}-host:append:p10bmc = " ${PN}-secure-check"
30 RRECOMMENDS:${PN}-chassis:append = " ${PN}-chassis-check-power-status"
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | lowlevel_init.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
53 push {r4-r12, lr} @ save registers - ROM code may pollute
60 smc 0 @ SMC #0 to enter monitor mode
62 pop {r4-r12, pc}
66 push {r4-r12, lr} @ save registers - ROM code may pollute
69 mov r12, #0x00 @ Secure Service ID in R12
73 smc 0 @ SMC #0 to enter monitor mode
78 @ In case of IRQ happening in Secure, then ARM will branch here.
79 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
85 smc 0 @ SMC #0 to enter monitor mode
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sec_entry_cpu1.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Secure entry function for CPU Core #1
35 * No need to save-restore registers, does not use stack.
42 mov r12, #0x00 @ Secure Service ID in R12
46 smc 0 @ SMC #0 to enter monitor mode
51 @ In case of IRQ happening in Secure, then ARM will branch here.
52 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
58 smc 0 @ SMC #0 to enter monitor mode
74 * Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
76 * u-boot.
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| /openbmc/linux/arch/arm/mach-highbank/ |
| H A D | smc.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copied from omap44xx-smc.S Copyright (C) 2010 Texas Instruments, Inc.
10 * This is common routine to manage secure monitor API
11 * used to modify the PL310 secure registers.
13 * the monitor API number.
16 .arch armv7-a
19 stmfd sp!, {r4-r11, lr}
24 ldmfd sp!, {r4-r11, pc}
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| /openbmc/linux/arch/arm/common/ |
| H A D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
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| /openbmc/u-boot/arch/arm/mach-meson/ |
| H A D | sm.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Secure monitor calls.
34 debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output); in meson_init_shmem()
50 return -1; in meson_sm_read_efuse()
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| /openbmc/qemu/docs/system/ |
| H A D | vnc-security.rst | 4 ------------
19 .. parsed-literal::
21 |qemu_system| [...OPTIONS...] -vnc unix:/home/joebloggs/.qemu-myvm-vnc
26 secure tunnel.
36 brute-forced by a client making repeat connections. For this reason, a
39 authentication is not supported when operating in FIPS 140-2 compliance
42 the password is set with the monitor. Until the monitor is used to set
45 .. parsed-literal::
47 |qemu_system| [...OPTIONS...] -vnc :1,password=on -monitor stdio
60 because TLS on its own is susceptible to man-in-the-middle attacks.
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Performance Monitor Units
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
[all …]
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