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/openbmc/u-boot/drivers/crypto/fsl/
H A Dsec.c1 // SPDX-License-Identifier: GPL-2.0+
14 * update crypto node properties to a specified revision of the SEC
17 #if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
27 { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ in fdt_fixup_crypto_node()
28 { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ in fdt_fixup_crypto_node()
29 { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ in fdt_fixup_crypto_node()
30 { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ in fdt_fixup_crypto_node()
31 { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ in fdt_fixup_crypto_node()
32 { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ in fdt_fixup_crypto_node()
33 { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ in fdt_fixup_crypto_node()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl-sec6.txt1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
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H A Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Freescale SEC 4
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
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/openbmc/linux/drivers/crypto/caam/
H A Dcaamalg_desc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2016-2019 NXP
14 * both of which are specified in req->src and req->dst
45 * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor
46 * (non-protocol) with no (null) encryption.
49 * A split key is required for SEC Era < 6; the size of the split key
50 * is specified in this case. Valid algorithm values - one of
54 * @era: SEC Era
57 unsigned int icvsize, int era) in cnstr_shdsc_aead_null_encap() argument
66 if (era < 6) { in cnstr_shdsc_aead_null_encap()
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H A Dcaamhash_desc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2017-2019 NXP
13 * cnstr_shdsc_ahash - ahash shared descriptor
16 * A split key is required for SEC Era < 6; the size of the split key
18 * Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
26 * @era: SEC Era
29 int digestsize, int ctx_len, bool import_ctx, int era) in cnstr_shdsc_ahash() argument
31 u32 op = adata->algtype; in cnstr_shdsc_ahash()
36 if (state != OP_ALG_AS_UPDATE && adata->keylen) { in cnstr_shdsc_ahash()
43 if (era < 6) in cnstr_shdsc_ahash()
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H A Ddpseci.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
10 * Data Path SEC Interface API
28 #define DPSECI_ALL_QUEUES (u8)(-1)
41 * struct dpseci_cfg - Structure representing DPSECI configuration
44 * @num_tx_queues: num of queues towards the SEC
45 * @num_rx_queues: num of queues back from the SEC
46 * @priorities: Priorities for the SEC hardware processing;
48 * towards the SEC;
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H A Dctrl.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
45 /* INIT RNG in non-test mode */ in build_instantiation_desc()
93 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
95 * @ctrldev - pointer to device
96 * @status - descriptor status, after being run
98 * Return: - 0 if no error occurred
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H A Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM/SEC 4.x driver backend
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
39 * Storage for tracking each in-process entry moving across a ring
60 /* Private sub-storage for a single JobR */
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H A Ddpseci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
12 * dpseci_open() - Open a control session for the specified object
38 cmd_params->dpseci_id = cpu_to_le32(dpseci_id); in dpseci_open()
49 * dpseci_close() - Close the control session of the object
70 * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames
88 * dpseci_disable() - Disable the DPSECI, stop sending and receiving frames
107 * dpseci_reset() - Reset the DPSECI, returns the object to initial state
125 * dpseci_is_enabled() - Check if the DPSECI is enabled.
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec6.0-0.dtsi2 * QorIQ Sec/Crypto 6.0 device tree stub
35 compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
36 "fsl,sec-v4.0";
37 fsl,sec-era = <6>;
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "fsl,sec-v6.0-job-ring",
43 "fsl,sec-v5.2-job-ring",
44 "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.4-job-ring",
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H A Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.0-job-ring";
69 compatible = "fsl,sec-v4.0-rtic";
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H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v4.2-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v4.2-job-ring",
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H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v5.0-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v5.0-job-ring",
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H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.2-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.2-job-ring",
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H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
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H A Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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/openbmc/u-boot/include/configs/
H A DM5235EVB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
42 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
64 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
69 #define CONFIG_BOOTFILE "u-boot.bin"
81 "u-boot=u-boot.bin\0" \
82 "load=tftp ${loadaddr) ${u-boot}\0" \
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H A DM5373EVB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
39 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
78 "u-boot=u-boot.bin\0" \
79 "load=tftp ${loadaddr) ${u-boot}\0" \
82 "era 0 3ffff;" \
103 /*-----------------------------------------------------------------------
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H A DM5329EVB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
39 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
78 "u-boot=u-boot.bin\0" \
79 "load=tftp ${loadaddr) ${u-boot}\0" \
82 "era 0 3ffff;" \
103 /*-----------------------------------------------------------------------
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H A DM5485EVB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
46 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
103 "u-boot=u-boot.bin\0" \
104 "load=tftp ${loadaddr) ${u-boot}\0" \
107 "era ff800000 ff83ffff;" \
130 /*-----------------------------------------------------------------------
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H A DM5475EVB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * board/config.h - configuration options, board specific
25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
46 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
115 "u-boot=u-boot.bin\0" \
116 "load=tftp ${loadaddr) ${u-boot}\0" \
119 "era ff800000 ff83ffff;" \
142 /*-----------------------------------------------------------------------
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