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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt8 Note that these settings are applied after any phy-specific fixup from
14 All skew control options are specified in picoseconds. The minimum
15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
23 The following table shows the actual skew delay you will get for each of the
25 corresponding pad skew register:
27 Device Tree Value Delay Pad Skew Register Value
28 -----------------------------------------------------
29 0 -840ps 0000
30 200 -720ps 0001
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt5 micrel-specific properties to an Ethernet OF device node.
7 Note that these settings are applied after any phy-specific fixup from
13 All skew control options are specified in picoseconds. The minimum
14 value is 0, the maximum value is 1800, and it is incremented by 120ps
19 - rxc-skew-ps : Skew control of RXC pad
20 - rxdv-skew-ps : Skew control of RX CTL pad
21 - txc-skew-ps : Skew control of TXC pad
22 - txen-skew-ps : Skew control of TX CTL pad
23 - rxd0-skew-ps : Skew control of RX data 0 pad
24 - rxd1-skew-ps : Skew control of RX data 1 pad
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3xmb_gmac.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard
13 phy-mode = "rgmii";
14 #address-cells = <1>;
15 #size-cells = <0>;
17 ethernet-phy@1 {
19 interrupt-parent = <&pioB>;
21 txen-skew-ps = <800>;
22 txc-skew-ps = <3000>;
23 rxdv-skew-ps = <400>;
[all …]
H A Dsama5d3xcm_cmp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module
9 compatible = "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5";
12 stdout-path = "serial0:115200n8";
21 clock-frequency = <32768>;
25 clock-frequency = <12000000>;
32 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
37 compatible = "atmel,tcb-timer";
42 compatible = "atmel,tcb-timer";
48 phy-mode = "rgmii";
[all …]
H A Dat91-dvk_su60_somc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board
12 compatible = "atmel,asoc-wm8904";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
16 atmel,model = "wm8904 @ DVK-SOM60";
17 atmel,audio-routing =
25 atmel,ssc-controller = <&ssc0>;
26 atmel,audio-codec = <&wm8904>;
35 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xcm.dtsi2 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
15 stdout-path = "serial0:115200n8";
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
35 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 phy-mode = "rgmii";
40 #address-cells = <1>;
41 #size-cells = <0>;
43 ethernet-phy@1 {
45 interrupt-parent = <&pioB>;
[all …]
H A Dsama5d3xcm_cmp.dtsi2 * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
38 phy-mode = "rgmii";
39 #address-cells = <1>;
40 #size-cells = <0>;
42 ethernet-phy@1 {
44 interrupt-parent = <&pioB>;
[all …]
H A Dsocfpga_cyclone5_de10_nano.dts1 // SPDX-License-Identifier: GPL-2.0+
11 model = "Terasic DE10-Nano";
12 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
31 u-boot,dm-pre-reloc;
37 phy-mode = "rgmii";
39 rxd0-skew-ps = <420>;
40 rxd1-skew-ps = <420>;
41 rxd2-skew-ps = <420>;
42 rxd3-skew-ps = <420>;
[all …]
H A Dsocfpga_cyclone5_de1_soc.dts1 // SPDX-License-Identifier: GPL-2.0+
9 model = "Terasic DE1-SoC";
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
29 u-boot,dm-pre-reloc;
35 phy-mode = "rgmii";
37 rxd0-skew-ps = <420>;
38 rxd1-skew-ps = <420>;
39 rxd2-skew-ps = <420>;
40 rxd3-skew-ps = <420>;
[all …]
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
16 stdout-path = "serial0:115200n8";
20 compatible = "gpio-leds";
40 u-boot,dm-pre-reloc;
50 phy-mode = "rgmii";
51 phy-handle = <&phy0>;
53 max-frame-size = <3800>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "snps,dwmac-mdio";
[all …]
H A Dsocfpga_cyclone5_de0_nano_soc.dts1 // SPDX-License-Identifier: GPL-2.0
9 model = "Terasic DE-0(Atlas)";
10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
27 regulator_3_3v: 3-3-v-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
[all …]
H A Dsocfpga_cyclone5_is1.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "anonymous,socfpga-is1", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
28 regulator_3_3v: 3-3-v-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "3.3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
36 u-boot,dm-pre-reloc;
42 phy-mode = "rgmii";
[all …]
H A Dsocfpga_arria10_socdk.dtsi21 compatible = "altr,socfpga-arria10", "altr,socfpga";
31 stdout-path = "serial0:115200n8";
38 u-boot,dm-pre-reloc;
42 compatible = "gpio-leds";
45 label = "a10sr-led0";
50 label = "a10sr-led1";
55 label = "a10sr-led2";
60 label = "a10sr-led3";
66 u-boot,dm-pre-reloc;
71 phy-mode = "rgmii";
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
53 regulator_3_3v: 3-3-v-regulator {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
63 phy-mode = "rgmii";
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
10 rxdv-skew-ps = <180>;
11 txen-skew-ps = <0>;
12 rxd3-skew-ps = <180>;
13 rxd2-skew-ps = <180>;
14 rxd1-skew-ps = <180>;
15 rxd0-skew-ps = <180>;
16 txd3-skew-ps = <120>;
[all …]
H A Dimx6q-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
10 pinctrl-names = "default";
11 pinctrl-0 = <&pinctrl_ecspi5_mba6x>;
12 cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
16 rxdv-skew-ps = <180>;
17 txen-skew-ps = <120>;
18 rxd3-skew-ps = <180>;
19 rxd2-skew-ps = <180>;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
25 stdout-path = "serial1:115200n8";
30 phy-mode = "rgmii";
31 phy-addr = <0xffffffff>; /* probe for phy addr */
33 max-frame-size = <3800>;
35 phy-handle = <&phy3>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 compatible = "snps,dwmac-mdio";
[all …]
H A Dsocfpga_cyclone5_de0_nano_soc.dts1 // SPDX-License-Identifier: GPL-2.0
9 model = "Terasic DE-0(Atlas)";
10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
36 led-hps0 {
[all …]
H A Dsocfpga_arria10_socdk.dtsi1 // SPDX-License-Identifier: GPL-2.0+
9 compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
31 label = "a10sr-led0";
36 label = "a10sr-led1";
41 label = "a10sr-led2";
46 label = "a10sr-led3";
51 ref_033v: 033-v-ref {
52 compatible = "regulator-fixed";
[all …]
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex_socdk_nand.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
39 compatible = "intel,easic-n5x-clkmgr";
44 phy-mode = "rgmii";
45 phy-handle = <&phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
[all …]
H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmicrel_ksz90x1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
18 * KSZ9021 - KSZ9031 common
52 phydev->duplex = DUPLEX_FULL; in ksz90xx_startup()
54 phydev->duplex = DUPLEX_HALF; in ksz90xx_startup()
57 phydev->speed = SPEED_1000; in ksz90xx_startup()
59 phydev->speed = SPEED_100; in ksz90xx_startup()
61 phydev->speed = SPEED_10; in ksz90xx_startup()
82 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
83 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
[all …]

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