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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
40 - items:
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec5.2-0.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.2-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.2-job-ring",
54 "fsl,sec-v5.0-job-ring",
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H A Dqoriq-sec5.3-0.dtsi36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
55 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-sec4.2-0.dtsi36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v4.2-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v4.2-job-ring",
60 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-sec5.0-0.dtsi36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v5.0-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v5.0-job-ring",
60 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-sec4.0-0.dtsi36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.0-job-ring";
68 rtic@6000 {
69 compatible = "fsl,sec-v4.0-rtic";
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H A Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2011
6 * (C) Copyright 2009 DENX Software Engineering
16 #include <asm/arch/imx-regs.h>
17 #include <generated/asm-offsets.h>
21 * AIPS setup - Only setup MPROTx registers.
25 * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
26 * user-mode.
39 * MAX (Multi-Layer AHB Crossbar Switch) setup
42 * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
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/openbmc/linux/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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/openbmc/linux/drivers/clk/imx/
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
154 /* CCM_CGCR0(29-31): reserved */ in __mx25_clocks_init()
191 /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */ in __mx25_clocks_init()
238 CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
897 /* Audio - I2S */
904 /* SPI Pre-Ratio */
1041 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1438 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
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