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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
27 equal to the number of Descriptor Controller (DECO) engines in a particular
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec5.2-0.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.2-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.2-job-ring",
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H A Dqoriq-sec5.3-0.dtsi25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
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H A Dqoriq-sec4.2-0.dtsi25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v4.2-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v4.2-job-ring",
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H A Dqoriq-sec5.0-0.dtsi25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v5.0-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v5.0-job-ring",
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H A Dqoriq-sec4.0-0.dtsi25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.0-job-ring";
68 rtic@6000 {
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H A Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
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/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_stream_id.h1 /* SPDX-License-Identifier: GPL-2.0+ */
27 * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
30 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
34 SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
39 /* This is a bit evil since we treat rtic param as both a string & hex value */
40 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ argument
41 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
43 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
45 CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
46 SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_liodn.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
35 + (port - 1) * 0x200 \
101 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
153 /* -1 from portID due to how immap has the registers */
156 offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
161 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
167 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
171 /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
173 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
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/openbmc/u-boot/include/
H A Dfsl_sec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define sec_in32(a) in_le32(a) argument
16 #define sec_out32(a, v) out_le32(a, v) argument
17 #define sec_in16(a) in_le16(a) argument
21 #define sec_in32(a) in_be32(a) argument
22 #define sec_out32(a, v) out_be32(a, v) argument
23 #define sec_in16(a) in_be16(a) argument
34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
88 u32 ms; /* RTIC LIODN Register, MS */
89 u32 ls; /* RTIC LIODN Register, LS */
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/openbmc/linux/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
23 * that (a) they can be contained in 32 bits, (b) if not, then they
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
162 * list of controller registers to be saved and restored during a
837 * bits. They are put into one because there is a need of
897 /* Audio - I2S */
904 /* SPI Pre-Ratio */
1041 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
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