| /openbmc/linux/Documentation/devicetree/bindings/leds/backlight/ |
| H A D | lp855x-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/lp855x-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Artur Weber <aweber.kernel@gmail.com>
15 - ti,lp8550
16 - ti,lp8551
17 - ti,lp8552
18 - ti,lp8553
19 - ti,lp8555
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| /openbmc/linux/arch/sh/include/mach-dreamcast/mach/ |
| H A D | sysasic.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/dreamcast/sysasic.h
8 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
15 #include <asm/irq.h>
17 /* Hardware events -
30 #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
32 #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
35 #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
36 #define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
41 /* arch/sh/boards/mach-dreamcast/irq.c */
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * plx9080.h
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/io.h>
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory.
14 #include "hw/sysbus.h"
15 #include "qom/object.h"
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/ |
| H A D | pxaregs.c | 2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
14 #include <stdio.h>
15 #include <unistd.h>
16 #include <stdlib.h>
17 #include <string.h>
18 #include <sys/mman.h>
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| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | siano-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 .. flat-table::
9 :header-rows: 1
11 :stub-columns: 0
13 * - Card name
14 - USB IDs
15 * - Hauppauge Catamount
16 - 2040:1700
17 * - Hauppauge Okemo-A
18 - 2040:1800
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9261.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
7 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
42 #define ATMEL_ID_TC2 19 /* Timer Counter 2 */
45 /* Reserved: 22-28 */
68 /* Reserved: 0xfffc4000 - 0xffffe9ff */
96 #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
97 #define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */
|
| H A D | at91sam9rl.h | 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
39 #define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
99 #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
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| /openbmc/linux/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g4.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <linux/bitops.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/mutex.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
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| /openbmc/linux/drivers/w1/ |
| H A D | w1_io.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <asm/io.h>
8 #include <linux/delay.h>
9 #include <linux/moduleparam.h>
10 #include <linux/module.h>
12 #include "w1_internal.h"
31 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | devices.txt | 1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
99 NOTE: The letter in the device name (d, q, h or u)
101 5.25" Quad Density (q), 5.25" High Density (h) or 3.5"
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| /openbmc/qemu/tests/qtest/ |
| H A D | i440fx-test.c | 4 * Copyright IBM, Corp. 2012-2013
12 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
17 #include "libqtest-single.h"
18 #include "libqos/pci.h"
19 #include "libqos/pci-pc.h"
20 #include "hw/pci/pci_regs.h"
30 /* decides whether we're testing -bios or -pflash */
38 cmdline = g_strdup_printf("-machine pc -smp %d", s->num_cpus); in test_start_get_bus()
77 if (s->num_cpus == 1) { /* WPE */ in test_i440fx_defaults()
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| /openbmc/qemu/hw/microblaze/ |
| H A D | xlnx-zynqmp-pmu.c | 18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "exec/address-spaces.h"
21 #include "hw/boards.h"
22 #include "cpu.h"
23 #include "boot.h"
25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
27 #include "qom/object.h"
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc"
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| /openbmc/linux/sound/soc/sof/intel/ |
| H A D | hda-loader-skl.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
6 // Copyright(c) 2018-2022 Intel Corporation. All rights reserved.
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/fs.h>
14 #include <linux/interrupt.h>
15 #include <linux/mm.h>
16 #include <linux/module.h>
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| /openbmc/linux/net/netrom/ |
| H A D | af_netrom.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/capability.h>
11 #include <linux/errno.h>
12 #include <linux/types.h>
13 #include <linux/socket.h>
14 #include <linux/in.h>
15 #include <linux/slab.h>
16 #include <linux/kernel.h>
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| /openbmc/linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_gsc_binary_headers.h | 1 /* SPDX-License-Identifier: MIT */
9 #include <linux/types.h>
26 /* size of pointers layout not including ROM bypass vector */
31 * bits1-15: reserved
66 * Bits 0-15: BPDT entry type
67 * Bits 16-17: reserved
68 * Bit 18: code sub-partition
69 * Bits 19-31: reserved
97 * Bits 0-24: offset from the beginning of the code partition
99 * Bits 26-31: reserved
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| /openbmc/u-boot/board/sunxi/ |
| H A D | README.sunxi64 | 1 Allwinner 64-bit boards README
4 Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for
5 both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode.
8 These SoCs are wired to start in AArch32 mode on reset and execute 32-bit
9 code from the Boot ROM (BROM). As this has some implications on U-Boot, this
10 file describes how to make full use of the 64-bit capabilities.
14 - Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
15 $ cd /src/arm-trusted-firmware
17 - Build U-Boot (see "SPL/U-Boot" below)
19 $ make pine64_plus_defconfig && make -j5
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| /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
13 #include <asm-offsets.h>
14 #include <config.h>
15 #include <mpc83xx.h>
16 #include <version.h>
21 #include <ppc_defs.h>
23 #include <asm/cache.h>
24 #include <asm/mmu.h>
25 #include <asm/u-boot.h>
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| /openbmc/linux/drivers/net/ethernet/alacritech/ |
| H A D | slic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/types.h>
7 #include <linux/netdevice.h>
8 #include <linux/spinlock_types.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/u64_stats_sync.h>
133 * 31-8 - phy addr of set of contiguous hdr buffers
134 * 7-0 - number of buffers passed
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| /openbmc/qemu/hw/m68k/ |
| H A D | q800.c | 23 #include "qemu/osdep.h"
24 #include "qemu/units.h"
25 #include "qemu/datadir.h"
26 #include "qemu/guest-random.h"
27 #include "sysemu/sysemu.h"
28 #include "cpu.h"
29 #include "hw/boards.h"
30 #include "hw/or-irq.h"
31 #include "elf.h"
32 #include "hw/loader.h"
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| /openbmc/u-boot/doc/ |
| H A D | README.x86 | 1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on x86
9 This document describes the information about U-Boot running on x86 targets,
13 ------
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
26 - Bayley Bay CRB
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| H A D | README.ae350 | 5 base on RISC-V architecture.
10 AX25-AE350
13 AX25-AE350 is the SoC with AE350 hardcore CPU.
19 If you want to boot this system from SPI ROM and bypass e-bios (the
20 other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
21 in "include/configs/ax25-ae350.h".
28 2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for 32 or 64 bit.
45 1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
46 2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
48 4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
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| /openbmc/u-boot/arch/x86/cpu/intel_common/ |
| H A D | me_status.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <common.h>
9 #include <asm/arch/me.h>
32 /* HFS[19:16] Current Operation Mode Values */
51 [ME_GMES_PHASE_ROM] = "ROM Phase",
62 [0x00] = "Clean Moff->Mx wake",
63 [0x01] = "Moff->Mx wake after an error",
68 [0x06] = "Pseudo-global reset",
69 [0x07] = "S0/M0->Sx/M3",
70 [0x08] = "Sx/M3->S0/M0",
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | cpm2_pic.c | 9 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
19 * There are two 32-bit registers (high/low) for up to 64
29 #include <linux/stddef.h>
30 #include <linux/sched.h>
31 #include <linux/signal.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
35 #include <asm/immap_cpm2.h>
36 #include <asm/io.h>
38 #include "cpm2_pic.h"
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| /openbmc/linux/drivers/firewire/ |
| H A D | core-card.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005-2007 Kristian Hoegsberg <krh@bitplanet.net>
6 #include <linux/bug.h>
7 #include <linux/completion.h>
8 #include <linux/crc-itu-t.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/firewire.h>
12 #include <linux/firewire-constants.h>
13 #include <linux/jiffies.h>
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