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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
H A Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP2)
10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
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H A Drockchip-drm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DRM master device
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The Rockchip DRM master device is a virtual device needed to list all
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
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H A Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
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H A Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
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H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
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/openbmc/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Rockchip"
16 Choose this option if you have a Rockchip soc chipset.
25 bool "Rockchip VOP driver"
28 This selects support for the VOP driver. You should enable it
32 bool "Rockchip VOP2 driver"
38 bool "Rockchip specific extensions for Analogix DP driver"
43 This selects support for Rockchip SoC specific extensions
48 bool "Rockchip cdn DP"
53 This selects support for Rockchip SoC specific extensions
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H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
44 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
46 * @lcdsel_big: reg value of selecting vop big for eDP
47 * @lcdsel_lit: reg value of selecting vop little for eDP
88 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
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H A Drockchip_vop2_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
126 * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
130 * Every esmart win and smart win support 4 Multi-region.
136 * * nearest-neighbor/bilinear/bicubic for scale up
137 * * nearest-neighbor/bilinear/average for scale down
140 * @TODO describe the wind like cpu-map dt nodes;
144 .name = "Smart0-win0",
157 .name = "Smart1-win0",
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H A Drockchip_vop_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
461 * hs_start interrupt fires at frame-start, so serves
569 * hs_start interrupt fires at frame-start, so serves
965 * rk3399 vop big windows register layout is same as rk3288, but we
1126 { .compatible = "rockchip,rk3036-vop",
1128 { .compatible = "rockchip,rk3126-vop",
1130 { .compatible = "rockchip,px30-vop-big",
1132 { .compatible = "rockchip,px30-vop-lit",
[all …]
H A Drockchip_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <mark.yao@rock-chips.com>
6 * Sandy Huang <hjc@rock-chips.com>
39 * struct rockchip_lvds_soc_data - rockchip lvds Soc private data
80 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
81 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
83 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
88 if (strncmp(s, "jeida-18", 8) == 0) in rockchip_lvds_name_to_format()
90 else if (strncmp(s, "jeida-24", 8) == 0) in rockchip_lvds_name_to_format()
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H A Drockchip_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
9 #include <linux/dma-mapping.h>
28 #include <asm/dma-iommu.h>
39 #define DRIVER_NAME "rockchip"
40 #define DRIVER_DESC "RockChip Soc DRM"
55 struct rockchip_drm_private *private = drm_dev->dev_private; in rockchip_drm_dma_attach_device()
58 if (!private->domain) in rockchip_drm_dma_attach_device()
70 ret = iommu_attach_device(private->domain, dev); in rockchip_drm_dma_attach_device()
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/openbmc/u-boot/drivers/video/rockchip/
H A Drk3288_vop.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2014 Rockchip Inc.
26 struct rk3288_vop *regs = priv->regs; in rk3288_set_pin_polarity()
28 /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ in rk3288_set_pin_polarity()
29 clrsetbits_le32(&regs->dsp_ctrl0, in rk3288_set_pin_polarity()
39 /* lcdc(vop) iodomain select 1.8V */ in rk3288_set_io_vsel()
40 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
59 if (!(gd->flags & GD_FLG_RELOC)) in rk3288_vop_probe()
62 /* Set the LCDC(vop) iodomain to 1.8V */ in rk3288_vop_probe()
65 /* Probe regulators required for the RK3288 VOP */ in rk3288_vop_probe()
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H A Drk3399_vop.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2014 Rockchip Inc.
23 struct rk3288_vop *regs = priv->regs; in rk3399_set_pin_polarity()
26 * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of in rk3399_set_pin_polarity()
31 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
37 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
43 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
66 if (!(gd->flags & GD_FLG_RELOC)) in rk3399_vop_probe()
69 /* Probe regulators required for the RK3399 VOP */ in rk3399_vop_probe()
86 { .compatible = "rockchip,rk3399-vop-big",
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H A Drk3288_mipi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Eric Gao <eric.gao@rock-chips.com>
19 #include <dm/uclass-internal.h>
28 /* Select mipi dsi source, big or little vop */
32 struct rk3288_grf *grf = priv->grf; in rk_mipi_dsi_source_select()
36 switch (disp_uc_plat->source_id) { in rk_mipi_dsi_source_select()
38 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
48 debug("%s: Invalid VOP id\n", __func__); in rk_mipi_dsi_source_select()
[all …]
H A Drk3399_mipi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Eric Gao <eric.gao@rock-chips.com>
19 #include <dm/uclass-internal.h>
26 /* Select mipi dsi source, big or little vop */
30 struct rk3399_grf_regs *grf = priv->grf; in rk_mipi_dsi_source_select()
34 switch (disp_uc_plat->source_id) { in rk_mipi_dsi_source_select()
36 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
40 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
44 debug("%s: Invalid VOP id\n", __func__); in rk_mipi_dsi_source_select()
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H A DKconfig2 # Video drivers selection for rockchip soc. These configs only impact the
6 # display by configure the device tree, and the vop driver will do the rest.
8 # Author: Eric Gao <eric.gao@rock-chips.com>
12 bool "Enable Rockchip Video Support"
15 Rockchip SoCs provide video output capabilities for High-Definition
16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
19 This driver supports the on-chip video output device, and targets the
20 Rockchip RK3288 and RK3399.
29 framebuffer during device-model binding/probing.
38 framebuffer during device-model binding/probing.
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H A Drk3288_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
27 int vop_id = uc_plat->source_id; in rk3288_hdmi_enable()
28 struct rk3288_grf *grf = priv->grf; in rk3288_hdmi_enable()
31 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
33 /* hdmi data from vop id */ in rk3288_hdmi_enable()
34 rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); in rk3288_hdmi_enable()
42 struct dw_hdmi *hdmi = &priv->hdmi; in rk3288_hdmi_ofdata_to_platdata()
44 hdmi->i2c_clk_high = 0x7a; in rk3288_hdmi_ofdata_to_platdata()
45 hdmi->i2c_clk_low = 0x8d; in rk3288_hdmi_ofdata_to_platdata()
48 * TODO(sjg@chromium.org): The above values don't work - these in rk3288_hdmi_ofdata_to_platdata()
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 compatible = "rockchip,rk3566";
10 compatible = "rockchip,rk3566-pipe-grf", "syscon";
14 power-domain@RK3568_PD_PIPE {
22 #power-domain-cells = <0>;
28 phy-names = "usb2-phy";
30 maximum-speed = "high-speed";
33 &vop {
34 compatible = "rockchip,rk3566-vop";
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
9 compatible = "rockchip,rk3568";
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
14 compatible = "rockchip,rk3066a";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
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H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
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