/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3188.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3188-cru.h> 10 #include <dt-bindings/power/rk3188-power.h> 14 compatible = "rockchip,rk3188"; 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 23 compatible = "arm,cortex-a9"; [all …]
|
H A D | rk3xxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/soc/rockchip,boot-mode.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 15 interrupt-parent = <&gic>; 33 compatible = "fixed-clock"; 34 clock-frequency = <24000000>; 35 #clock-cells = <0>; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | rockchip,rk3188-cru.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 14 The RK3188/RK3066 clock controller generates and supplies clocks to various 19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and 20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. [all …]
|
/openbmc/u-boot/doc/device-tree-bindings/clock/ |
H A D | rockchip,rk3188-cru.txt | 1 * Rockchip RK3188/RK3066 Clock and Reset Unit 3 The RK3188/RK3066 clock controller generates and supplies clock to various 9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or 10 "rockchip,rk3066a-cru" 11 - reg: physical base address of the controller and length of memory mapped 13 - #clock-cells: should be 1. 14 - #reset-cells: should be 1. 18 - rockchip,grf: phandle to the syscon managing the "general register files" 23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and 24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. [all …]
|
H A D | rockchip,rk3288-cru.txt | 9 - compatible: should be "rockchip,rk3288-cru" 10 - reg: physical base address of the controller and length of memory mapped 12 - #clock-cells: should be 1. 13 - #reset-cells: should be 1. 17 - rockchip,grf: phandle to the syscon managing the "general register files" 22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be 30 clock-output-names: 31 - "xin24m" - crystal input - required, 32 - "xin32k" - rtc clock - optional, 33 - "ext_i2s" - external I2S clock - optional, [all …]
|
/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3188.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR X11 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3188-cru.h> 13 compatible = "rockchip,rk3188"; 16 #address-cells = <1>; 17 #size-cells = <0>; 18 enable-method = "rockchip,rk3066-smp"; 22 compatible = "arm,cortex-a9"; 23 next-level-cache = <&L2>; [all …]
|
H A D | rk3xxx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR X11 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 interrupt-parent = <&gic>; 33 compatible = "simple-bus"; 34 #address-cells = <1>; 35 #size-cells = <1>; 38 dmac1_s: dma-controller@20018000 { 43 #dma-cells = <1>; 44 arm,pl330-broken-no-flushp; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | rockchip,emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3036/RK3066/RK3188 Ethernet Media Access Controller (EMAC) 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,rk3036-emac 16 - rockchip,rk3066-emac 17 - rockchip,rk3188-emac 28 - description: host clock 29 - description: reference clock [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | rockchip-spdif.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Heiko Stuebner <heiko@sntech.de> 20 - const: rockchip,rk3066-spdif 21 - const: rockchip,rk3228-spdif 22 - const: rockchip,rk3328-spdif 23 - const: rockchip,rk3366-spdif 24 - const: rockchip,rk3368-spdif [all …]
|
H A D | rockchip-i2s.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The I2S bus (Inter-IC sound bus) is a serial link for digital 14 - Heiko Stuebner <heiko@sntech.de> 17 - $ref: dai-common.yaml# 22 - const: rockchip,rk3066-i2s 23 - items: 24 - enum: [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | i2c-rk3x.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - $ref: /schemas/i2c/i2c-controller.yaml# 17 - Heiko Stuebner <heiko@sntech.de> 23 - const: rockchip,rv1108-i2c 24 - const: rockchip,rk3066-i2c 25 - const: rockchip,rk3188-i2c 26 - const: rockchip,rk3228-i2c [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/ |
H A D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 15 - items: 16 - enum: 17 - rockchip,rk3288-sgrf 18 - rockchip,rk3566-pipe-grf 19 - rockchip,rk3568-pcie3-phy-grf 20 - rockchip,rk3568-pipe-grf [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
H A D | rockchip-efuse.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 13 - $ref: nvmem.yaml# 18 - rockchip,rk3066a-efuse 19 - rockchip,rk3188-efuse 20 - rockchip,rk3228-efuse 21 - rockchip,rk3288-efuse [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | spi-rockchip.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - $ref: spi-controller.yaml# 17 - Heiko Stuebner <heiko@sntech.de> 23 - const: rockchip,rk3036-spi 24 - const: rockchip,rk3066-spi 25 - const: rockchip,rk3228-spi 26 - const: rockchip,rv1108-spi [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/power/ |
H A D | rockchip,power-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 18 Power domains contained within power-controller node are 20 Documentation/devicetree/bindings/power/power-domain.yaml. 23 "power-domains" property that is a phandle for the 28 const: power-controller [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/mtd/ |
H A D | rockchip,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - $ref: nand-controller.yaml# 13 - Heiko Stuebner <heiko@sntech.de> 18 - const: rockchip,px30-nfc 19 - const: rockchip,rk2928-nfc 20 - const: rockchip,rv1108-nfc 21 - items: [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip-vop.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Sandy Huang <hjc@rock-chips.com> 16 - Heiko Stuebner <heiko@sntech.de> 21 - rockchip,px30-vop-big 22 - rockchip,px30-vop-lit 23 - rockchip,rk3036-vop 24 - rockchip,rk3066-vop [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | rockchip-vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Ezequiel Garcia <ezequiel@collabora.com> 19 - enum: 20 - rockchip,rk3036-vpu 21 - rockchip,rk3066-vpu 22 - rockchip,rk3288-vpu 23 - rockchip,rk3328-vpu [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | rockchip,rk-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daniel Lezcano <daniel.lezcano@linaro.org> 15 - const: rockchip,rk3288-timer 16 - const: rockchip,rk3399-timer 17 - items: 18 - enum: 19 - rockchip,rv1108-timer [all …]
|
/openbmc/u-boot/drivers/ram/rockchip/ |
H A D | sdram_rk3188.c | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 12 #include <dt-structs.h> 37 struct rk3188_cru *cru; member 95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() argument 103 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset() 112 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) in ddr_phy_ctl_reset() argument 116 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset() 120 static void phy_pctrl_reset(struct rk3188_cru *cru, in phy_pctrl_reset() argument 126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset() 128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset() [all …]
|
/openbmc/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3188.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <clk-uclass.h> 10 #include <dt-structs.h> 19 #include <dt-bindings/clock/rk3188-cru.h> 20 #include <dm/device-internal.h> 22 #include <dm/uclass-internal.h> 85 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument 89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() 91 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll() 92 uint output_hz = vco_hz / div->no; in rkclk_set_pll() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/pwm/ |
H A D | pwm-rockchip.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 15 - const: rockchip,rk2928-pwm 16 - const: rockchip,rk3288-pwm 17 - const: rockchip,rk3328-pwm 18 - const: rockchip,vop-pwm 19 - items: [all …]
|
/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | rk3066a-cru.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 10 #include <dt-bindings/clock/rk3188-cru-common.h> 12 /* soft-reset indices */
|
H A D | rk3188-cru.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 10 #include <dt-bindings/clock/rk3188-cru-common.h> 12 /* soft-reset indices */
|
/openbmc/linux/include/dt-bindings/clock/ |
H A D | rk3066a-cru.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 10 #include <dt-bindings/clock/rk3188-cru-common.h> 12 /* soft-reset indices */
|