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/openbmc/linux/drivers/phy/motorola/
H A Dphy-mapphone-mdm6600.c1 // SPDX-License-Identifier: GPL-2.0
3 * Motorola Mapphone MDM6600 modem GPIO controlled USB PHY driver
18 #include <linux/phy/phy.h>
21 #define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
23 #define PHY_MDM6600_WAKE_KICK_MS 600 /* time on after GPIO toggle */
28 PHY_MDM6600_ENABLE, /* USB PHY enable */
30 PHY_MDM6600_RESET, /* Device reset */
35 PHY_MDM6600_MODE0, /* out USB mode0 and OOB wake */
36 PHY_MDM6600_MODE1, /* out USB mode1, in OOB wake */
55 * MDM6600 command codes. These are based on Motorola Mapphone Linux
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
24 stdout-path = "serial0:1500000n8";
28 compatible = "gpio-leds";
29 pinctrl-names = "default";
30 pinctrl-0 = <&green_led>, <&heartbeat_led>;
32 green-led {
34 default-state = "on";
38 linux,default-trigger = "default-on";
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H A Drk3566-box-demo.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,vop2.h>
18 compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
28 stdout-path = "serial2:1500000n8";
31 gmac1_clkin: external-gmac1-clock {
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H A Drk3328-a1.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (c) 2017-2019 Arm Ltd.
4 /dts-v1/;
9 compatible = "azw,beelink-a1", "rockchip,rk3328";
20 * /-------
21 * L / o <- Gnd
22 * e / o <-- Rx
23 * f / o <--- Tx
24 * t / o <---- +3.3v
28 stdout-path = "serial2:1500000n8";
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H A Drk3399-orangepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/pwm/pwm.h"
9 #include "dt-bindings/input/input.h"
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3399-opp.dtsi"
17 compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
26 stdout-path = "serial2:1500000n8";
29 clkin_gmac: external-gmac-clock {
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
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H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
8 at least a control module node, USB node and a PHY node. The second USB
9 node and its PHY node are optional. The DMA node is also optional.
11 Reset module
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
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/openbmc/linux/drivers/char/tpm/
H A Dtpm_tis_spi_cr50.c1 // SPDX-License-Identifier: GPL-2.0
7 * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard.
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
55 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) in to_cr50_spi_phy() argument
57 return container_of(phy, struct cr50_spi_phy, spi_phy); in to_cr50_spi_phy()
69 cr50_phy->irq_confirmed = true; in cr50_spi_irq_handler()
70 complete(&cr50_phy->spi_phy.ready); in cr50_spi_irq_handler()
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-fievel.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-analog-audio.dtsi"
14 compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
15 "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
16 "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
17 "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
18 "google,veyron-fievel-rev0", "google,veyron-fievel",
22 compatible = "regulator-fixed";
[all …]
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = "serial2:115200n8";
22 * The default coreboot on veyron devices ignores memory@0 nodes
31 power_button: power-button {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pwr_key_l>;
36 key-power {
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/openbmc/linux/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet_wol.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) Wake-on-LAN support
5 * Copyright (c) 2014-2024 Broadcom
33 #include <linux/phy.h>
37 /* ethtool function - get WOL (Wake on LAN) settings, Only Magic Packet
43 struct device *kdev = &priv->pdev->dev; in bcmgenet_get_wol()
46 if (dev->phydev) { in bcmgenet_get_wol()
47 phy_ethtool_get_wol(dev->phydev, wol); in bcmgenet_get_wol()
48 phy_wolopts = wol->wolopts; in bcmgenet_get_wol()
51 /* MAC is not wake-up capable, return what the PHY does */ in bcmgenet_get_wol()
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/openbmc/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_ (0x00040000) /* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_ (0x00008000) /* PHY Interrupt */
83 #define HW_CFG_LRST_ (0x00000008) /* Soft Lite Reset */
84 #define HW_CFG_PSEL_ (0x00000004) /* External PHY Select */
86 #define HW_CFG_SRST_ (0x00000001) /* Soft Reset */
106 #define PM_CTL_PHY_RST_ (0x00000010) /* PHY Reset */
107 #define PM_CTL_WOL_EN_ (0x00000008) /* Wake On Lan Enable */
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/openbmc/linux/drivers/usb/dwc2/
H A Dplatform.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * platform.c - DesignWare HS OTG Controller platform driver
13 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_data/s3c-hsotg.h>
19 #include <linux/reset.h>
39 * ------------------------------
41 * HST DEV any : ---
44 * DEV HST any : ---
56 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); in dwc2_get_dr_mode()
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/openbmc/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
41 u32 RESET; member
105 #define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */
106 #define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */
116 /* Reset */
117 #define PCH_GBE_ALL_RST 0x80000000 /* All reset */
118 #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
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/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
12 /* Wake Up Control */
15 /* Wake Up Filter Control */
22 /* Wake Up Status */
29 /* Packet types that are enabled for wake packet delivery */
37 /* Wake Up Packet Length */
40 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
49 /* Physical Func Reset Done Indication */
62 /* Interrupt acknowledge Auto-mask */
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/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 /* Wake Up Control */
19 /* Wake Up Filter Control */
39 /* Wake Up Status */
46 /* Packet types that are enabled for wake packet delivery */
54 /* Wake Up Packet Length */
57 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
130 #define IGC_CTRL_RST 0x04000000 /* Global reset */
132 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
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/openbmc/linux/drivers/net/phy/
H A Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
13 #include "bcm-phy-lib.h"
16 #include <linux/phy.h>
25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
30 MODULE_DESCRIPTION("Broadcom PHY driver");
43 struct bcm54xx_phy_priv *priv = phydev->priv; in bcm54xx_phy_can_wakeup()
45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()
52 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
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/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
20 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
32 label = "nanopi-k2:blue:stat";
34 default-state = "on";
35 panic-indicator;
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/openbmc/linux/drivers/usb/phy/
H A Dphy-tegra-usb.c1 // SPDX-License-Identifier: GPL-2.0
221 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) in set_pts() argument
223 void __iomem *base = phy->regs; in set_pts()
226 if (phy->soc_config->has_hostpc) { in set_pts()
240 static void set_phcd(struct tegra_usb_phy *phy, bool enable) in set_phcd() argument
242 void __iomem *base = phy->regs; in set_phcd()
245 if (phy->soc_config->has_hostpc) { in set_phcd()
262 static int utmip_pad_open(struct tegra_usb_phy *phy) in utmip_pad_open() argument
266 ret = clk_prepare_enable(phy->pad_clk); in utmip_pad_open()
268 dev_err(phy->u_phy.dev, in utmip_pad_open()
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/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-g12b-bananapi.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
21 stdout-path = "serial0:115200n8";
29 adc-keys {
30 compatible = "adc-keys";
31 io-channels = <&saradc 2>;
32 io-channel-names = "buttons";
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
H A Dsc8280xp-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sc8280xp-pmics.dtsi"
17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
26 compatible = "pwm-backlight";
28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
29 power-supply = <&vreg_edp_bl>;
31 pinctrl-names = "default";
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*-
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
13 #include <generic-phy.h>
15 /* Section 2.2.3 - N_PORTS */
37 #define CMD_LRESET (1 << 7) /* partial reset */
41 #define CMD_RESET (1 << 1) /* reset HC not bus */
52 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
122 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
123 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
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