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Searched full:reg_clock (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/timer/
H A Dcadence_ttc.c77 if (s->reg_clock & CLOCK_CTRL_PS_EN) { in cadence_timer_get_ns()
78 r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); in cadence_timer_get_ns()
104 if (s->reg_clock & CLOCK_CTRL_PS_EN) { in cadence_timer_get_steps()
105 r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); in cadence_timer_get_steps()
219 return s->reg_clock; in cadence_ttc_read_imp()
302 s->reg_clock = value & 0x3F; in cadence_ttc_write()
429 VMSTATE_UINT32(reg_clock, CadenceTimerState),
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-sx150x.c70 u8 reg_clock; member
292 .reg_clock = 0x0d,
313 .reg_clock = 0x0f,
334 .reg_clock = 0x1e,
431 pctl->data->pri.x789.reg_clock, in sx150x_gpio_oscio_set()
615 pctl->data->pri.x789.reg_clock, in sx150x_pinconf_get()
952 reg == data->pri.x789.reg_clock || in sx150x_regmap_reg_width()
/openbmc/qemu/include/hw/timer/
H A Dcadence_ttc.h28 uint32_t reg_clock; member
/openbmc/u-boot/drivers/spi/
H A Dmeson_spifc.c26 #define REG_CLOCK 0x18 macro
237 regmap_write(spifc->regmap, REG_CLOCK, value); in meson_spifc_set_speed()
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmarvell,mv64xxx-i2c.yaml138 clocks = <&core_clock>, <&reg_clock>;
/openbmc/linux/drivers/spi/
H A Dspi-meson-spifc.c28 #define REG_CLOCK 0x18 macro
181 regmap_write(spifc->regmap, REG_CLOCK, value); in meson_spifc_setup_speed()