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/openbmc/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
42 /* Threshold to exit fixed refresh rate */
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
71 core_freesync->dc = dc; in mod_freesync_create()
72 return &core_freesync->public; in mod_freesync_create()
117 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
118 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
135 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-hid-picolcd1 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
3 Contact: Bruno Prémont <bonbons@linux-vserver.org>
11 the non-active mode names listed when read.
18 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
20 Contact: Bruno Prémont <bonbons@linux-vserver.org>
28 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
30 Contact: Bruno Prémont <bonbons@linux-vserver.org>
31 Description: Make it possible to adjust defio refresh rate.
33 Reading: returns list of available refresh rates (expressed in Hz),
34 the active refresh rate being enclosed in brackets ('[' and ']')
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/openbmc/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dholtek,ht16k33.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robin van der Gracht <robin@protonic.nl>
13 - $ref: /schemas/input/matrix-keymap.yaml#
18 - items:
19 - enum:
20 - adafruit,3108 # 0.56" 4-Digit 7-Segment FeatherWing Display (Red)
21 - adafruit,3130 # 0.54" Quad Alphanumeric FeatherWing Display (Red)
22 - const: holtek,ht16k33
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/openbmc/linux/Documentation/fb/
H A Duvesafb.rst2 uvesafb - A Generic Driver for VBE2+ compliant video cards
6 ---------------
30 --------------------------
36 - Lack of any type of acceleration.
37 - A strict and limited set of supported video modes. Often the native
38 or most optimal resolution/refresh rate for your setup will not work
42 ratio, which is what most BIOS-es are limited to.
43 - Adjusting the refresh rate is only possible with a VBE 3.0 compliant
44 Video BIOS. Note that many nVidia Video BIOS-es claim to be VBE 3.0
45 compliant, while they simply ignore any refresh rate settings.
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H A Dmodedb.rst9 - one routine to probe for video modes, which can be used by all frame buffer
11 - one generic video mode database with a fair amount of standard videomodes
13 - the possibility to supply your own mode database for graphics hardware that
14 needs non-standard modes, like amifb and Mac frame buffer drivers (which
23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
31 - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
32 - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
34 - PAL: 576i output, with the CCIR System-B TV mode and PAL color encoding
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H A Dintel810.rst20 - Intel 810
21 - Intel 810E
22 - Intel 810-DC100
23 - Intel 815 Internal graphics only, 100Mhz FSB
24 - Intel 815 Internal graphics only
25 - Intel 815 Internal graphics and AGP
30 - Choice of using Discrete Video Timings, VESA Generalized Timing
33 - Supports a variable range of horizontal and vertical resolution and
34 vertical refresh rates if the VESA Generalized Timing Formula is
37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
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/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c2 * linux/drivers/video/modedb.c -- Standard video mode database management
6 * 2001 - Documented with DocBook
7 * - Brad Douglas <brad@neruo.com>
38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
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H A Dfbcvt.c2 * linux/drivers/video/fbcvt.c - VESA(TM) Coordinated Video Timings
38 u32 refresh; member
75 u32 num = 1000000000/cvt->f_refresh; in fb_cvt_hperiod()
78 if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK) { in fb_cvt_hperiod()
79 num -= FB_CVT_RB_MIN_VBLANK * 1000; in fb_cvt_hperiod()
80 den = 2 * (cvt->yres/cvt->interlace + 2 * cvt->v_margin); in fb_cvt_hperiod()
82 num -= FB_CVT_MIN_VSYNC_BP * 1000; in fb_cvt_hperiod()
83 den = 2 * (cvt->yres/cvt->interlace + cvt->v_margin * 2 in fb_cvt_hperiod()
84 + FB_CVT_MIN_VPORCH + cvt->interlace/2); in fb_cvt_hperiod()
93 u32 c_prime = (FB_CVT_GTF_C - FB_CVT_GTF_J) * in fb_cvt_ideal_duty_cycle()
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H A Dfbmon.c11 * Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved.
14 * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
62 /* DEC FR-PCXAV-YZ */
93 while (i-- && (*--s == 0x20)) *s = 0; in copy_string()
240 b[9] = 17; /* pixclock - 170 MHz*/ in fix_edid()
248 for (i = 0; i < EDID_LENGTH - 1; i++) in fix_edid()
251 edid[127] = 256 - csum; in fix_edid()
294 specs->manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@'; in parse_vendor_block()
295 specs->manufacturer[1] = ((block[0] & 0x03) << 3) + in parse_vendor_block()
297 specs->manufacturer[2] = (block[1] & 0x1f) + '@'; in parse_vendor_block()
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/openbmc/openbmc/meta-nuvoton/recipes-nuvoton/program-edid/program-edid/
H A Dedid.json8 "DPM active-off supported": true,
18 "Preferred timing includes native timing pixel format and refresh rate": true,
70 "Horizontal sync (outside of V-sync)": "Positive",
105 "Horizontal sync (outside of V-sync)": "Positive",
112 "Horizontal rate (kHz)": {
119 "Vertical rate (Hz)": {
130 "1024x768 @ 60 Hz": true,
131 "1024x768 @ 72 Hz": true,
132 "1024x768 @ 75 Hz": true,
133 "1024x768 @ 87 Hz, interlaced (1024x768i)": false,
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/openbmc/linux/arch/arm/mach-omap2/
H A Dsdrc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
56 * @rate: SDRC clock rate (in Hz)
57 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
58 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
59 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
60 * @mr: Value to program to SDRC_MR for this rate
62 * This structure holds a pre-computed set of register values for the
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/openbmc/linux/drivers/staging/sm750fb/
H A Dreadme4 - dual display
5 - 2D acceleration
6 - 16MB integrated video memory
10 Use 1280,8bpp index color and 60 hz mode:
11 insmod ./sm750fb.ko g_option="1280x1024-8@60"
23 1) if you build the driver with built-in method, the parameter
33 refresh rate, kernel driver will defaulty use 16bpp and 60hz
37 and this driver will use fb1, fb2. In that case, you need to configure your X-server
/openbmc/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/openbmc/linux/drivers/memory/
H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
105 /* MR4 SDRAM Refresh Rate field values */
207 * -ENOENT if info unavailable.
223 * are in Hz.
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enumstd.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_ENUMSTD - VIDIOC_SUBDEV_ENUMSTD - Enumerate supported video standards
52 .. flat-table:: struct v4l2_standard
53 :header-rows: 0
54 :stub-columns: 0
57 * - __u32
58 - ``index``
59 - Number of the video standard, set by the application.
60 * - :ref:`v4l2_std_id <v4l2-std-id>`
61 - ``id``
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/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Demc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
41 u32 refresh; /* 0x70: EMC_REFRESH */ member
78 * Set up the EMC for the given rate. The timing parameters are retrieved
79 * from the device tree "nvidia,tegra20-emc" node and its
80 * "nvidia,tegra20-emc-table" sub-nodes.
83 * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
84 * @return 0 if ok, else -ve error code (look in emc.c to decode it)
86 int tegra_set_emc(const void *blob, unsigned rate);
/openbmc/linux/drivers/video/fbdev/
H A Dcontrolfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
52 struct preg hperiod; /* horiz period - 2 */
59 struct preg hserr; /* horiz period - horiz sync len */
67 struct preg rfrcnt; /* refresh count */
85 unsigned hperiod; /* horiz period - 2 */
92 unsigned hserr; /* horiz period - horiz sync len */
96 * Dot clock rate is
120 {{-1,-1}}, /* 512x384, 60Hz interlaced (NTSC) */
121 {{-1,-1}}, /* 512x384, 60Hz */
122 {{-1,-1}}, /* 640x480, 50Hz interlaced (PAL) */
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/openbmc/u-boot/drivers/video/
H A Dvideomodes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
38 int refresh; /* vertical refresh rate in hz */ member
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv.c2 * Copyright © 2006-2008 Intel Corporation
30 * Integrated TV-out support for the 915GM and 945GM.
134 * ee = 00 = 10^-1 (0.mmmmmmmmm)
135 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
136 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
137 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
140 * eee = 000 = 10^-1 (0.mmmmmmmmm)
141 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
142 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
143 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_mdss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \
55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \
58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
295 * enum dpu_plane_type - defines how the color component pixel packing
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
60 * (access to non-DC registers will hang FPGA) */
146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
229 /* note: part of refresh rate flag*/
247 /* Refresh rate divider when Miracast sink is using a
248 different rate than the output display device
249 Must be zero for wired displays and non-zero for
318 /* Vertical refresh rate for progressive modes.
319 * Field rate for interlaced modes.*/
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/openbmc/linux/include/drm/
H A Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
46 * enum drm_mode_status - hardware support status of a mode
129 MODE_STALE = -3,
130 MODE_BAD = -2,
131 MODE_ERROR = -1
142 * DRM_MODE_RES_MM - Calculates the display size from resolution and DPI
157 * DRM_MODE_INIT - Initialize display mode
158 * @hz: Vertical refresh rate in Hertz
165 * refresh rate, resolution and physical size.
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/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Demc.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/ap.h>
10 #include <asm/arch-tegra/apb_misc.h>
47 0x70, /* REFRESH */
94 ERR_NO_EMC_NODE = -10,
107 * We detect which is in use by looking for the nvidia,use-ram-code property.
109 * otherwise we select the correct emc-tables subnode based on the 'ram_code'
113 * @param node EMC node (nvidia,tegra20-emc compatible string)
114 * @param ram_code RAM code to select (0-3, or -1 if unknown)
115 * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
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