| /openbmc/linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000InitDevice.c | 117 u32 ProgramClock(u32 refClock, in ProgramClock() argument
131 refClock *= 1000; /* in Hz */ in ProgramClock()
153 F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER)); in ProgramClock()
168 ulVCO = refClock / R; in ProgramClock()
186 …ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K… in ProgramClock()
|
| H A D | STG4000Interface.h | 37 extern u32 ProgramClock(u32 refClock, u32 coreClock, u32 *FOut, u32 *ROut, u32 *POut);
|
| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | fsl,imx8-pcie-phy.yaml | 46 refclock is derived from SoC internal source), INPUT(PHY refclock
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
|
| H A D | ti,phy-j721e-wiz.yaml | 147 WIZ node should have subnodes for each of the PMA common refclock
|
| /openbmc/u-boot/include/linux/ |
| H A D | mc146818rtc.h | 48 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
53 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
|
| /openbmc/linux/drivers/media/tuners/ |
| H A D | mt2063.h | 9 u32 refclock; member
|
| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | cdns,rtc.txt | 21 clocks = <&sysclock>, <&refclock>;
|
| /openbmc/linux/include/linux/ |
| H A D | mc146818rtc.h | 77 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
82 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
|
| /openbmc/openbmc/meta-ibm/recipes-support/chrony/chrony/huygens/ |
| H A D | chrony.conf | 8 #refclock PPS /dev/pps0 poll 0 prefer
|
| /openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/chrony/chrony/ |
| H A D | chrony.conf | 15 #refclock PPS /dev/pps0 poll 0 prefer
|
| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | stb6100.h | 68 u32 refclock; member
|
| H A D | stv6110x.c | 231 static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock) in stv6110x_set_refclock() argument
236 switch (refclock) { in stv6110x_set_refclock()
|
| /openbmc/skeleton/configs/ |
| H A D | Palmetto.py | 54 0x37: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Romulus.py | 54 "<inventory_root>/system/chassis/motherboard/refclock": {
474 0x8D: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Witherspoon.py | 55 "<inventory_root>/system/chassis/motherboard/refclock": {
523 0x0D: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Garrison.py | 56 "<inventory_root>/system/chassis/motherboard/refclock": {
524 0x63: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Zaius.py | 55 "<inventory_root>/system/chassis/motherboard/refclock": {
586 0x11: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Lanyang.py | 55 "<inventory_root>/system/chassis/motherboard/refclock": {
586 0x11: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Firestone.py | 56 "<inventory_root>/system/chassis/motherboard/refclock": {
524 0x63: "<inventory_root>/system/chassis/motherboard/refclock",
|
| /openbmc/openbmc-test-automation/data/ |
| H A D | Palmetto.py | 287 "<inventory_root>/system/chassis/motherboard/refclock": {
330 0x37: "<inventory_root>/system/chassis/motherboard/refclock",
|
| H A D | Witherspoon.py | 57 "<inventory_root>/system/chassis/motherboard/refclock": {
525 0x0D: "<inventory_root>/system/chassis/motherboard/refclock",
|
| /openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/ntpsec/ |
| H A D | ntpsec_1.2.2a.bb | 45 PACKAGECONFIG[refclocks] = "--refclock=all,,pps-tools"
|
| /openbmc/linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8m-pcie.c | 103 /* Configure the PHY to output the refclock via pad */ in imx8_pcie_phy_power_on()
|
| /openbmc/linux/drivers/media/pci/mantis/ |
| H A D | mantis_vp1041.c | 293 .refclock = 27000000,
|
| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-pcie2.c | 81 /* Don't use PAD for refclock */ in qcom_pcie2_phy_power_on()
|