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Searched full:refclock (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/include/linux/
H A Dmc146818rtc.h48 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
53 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
/openbmc/openbmc/meta-ibm/recipes-support/chrony/chrony/huygens/
H A Dchrony.conf8 #refclock PPS /dev/pps0 poll 0 prefer
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/chrony/chrony/
H A Dchrony.conf15 #refclock PPS /dev/pps0 poll 0 prefer
/openbmc/skeleton/configs/
H A DPalmetto.py54 0x37: "<inventory_root>/system/chassis/motherboard/refclock",
H A DRomulus.py54 "<inventory_root>/system/chassis/motherboard/refclock": {
474 0x8D: "<inventory_root>/system/chassis/motherboard/refclock",
H A DWitherspoon.py55 "<inventory_root>/system/chassis/motherboard/refclock": {
523 0x0D: "<inventory_root>/system/chassis/motherboard/refclock",
H A DGarrison.py56 "<inventory_root>/system/chassis/motherboard/refclock": {
524 0x63: "<inventory_root>/system/chassis/motherboard/refclock",
H A DZaius.py55 "<inventory_root>/system/chassis/motherboard/refclock": {
586 0x11: "<inventory_root>/system/chassis/motherboard/refclock",
H A DLanyang.py55 "<inventory_root>/system/chassis/motherboard/refclock": {
586 0x11: "<inventory_root>/system/chassis/motherboard/refclock",
H A DFirestone.py56 "<inventory_root>/system/chassis/motherboard/refclock": {
524 0x63: "<inventory_root>/system/chassis/motherboard/refclock",
H A DBarreleye.py73 "<inventory_root>/system/chassis/motherboard/refclock": {
520 0x37: "<inventory_root>/system/chassis/motherboard/refclock",
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/ntpsec/
H A Dntpsec_1.2.2a.bb45 PACKAGECONFIG[refclocks] = "--refclock=all,,pps-tools"
/openbmc/openbmc-test-automation/data/
H A DPalmetto.py287 "<inventory_root>/system/chassis/motherboard/refclock": {
330 0x37: "<inventory_root>/system/chassis/motherboard/refclock",
H A DWitherspoon.py57 "<inventory_root>/system/chassis/motherboard/refclock": {
525 0x0D: "<inventory_root>/system/chassis/motherboard/refclock",
H A DRomulus.py56 "<inventory_root>/system/chassis/motherboard/refclock": {
478 0x8D: "<inventory_root>/system/chassis/motherboard/refclock",
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dspeed.c92 * are driven by separate DDR Refclock or single source in get_sys_info()
H A Dfsl_corenet_serdes.c386 /* Determine refclock from XAUI ratio */ in p4080_erratum_serdes8()
/openbmc/u-boot/drivers/pci/
H A Dpci_tegra.c683 * Set up PHY PLL inputs select PLLE output as refclock, set TX in tegra_pcie_phy_enable()