Home
last modified time | relevance | path

Searched +full:r8a7790 +full:- +full:cmt1 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7790.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the r8a7790 SoC
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7790-sysc.h>
16 compatible = "renesas,r8a7790";
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7790.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H2 (R8A77900) SoC
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7790-sysc.h>
16 compatible = "renesas,r8a7790";
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7790-cpg-mssr.c2 * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
6 * Based on clk-rcar-gen2.c
16 #include <clk-uclass.h>
19 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
103 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
104 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
105 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
106 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr8a7790-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
7 * Based on clk-rcar-gen2.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen2-cpg.h"
101 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
102 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
103 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
[all …]
/openbmc/linux/drivers/clocksource/
H A Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
239 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
[all …]