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/openbmc/linux/drivers/watchdog/
H A Die6xx_wdt.c23 #define PV1 0x00 macro
118 outl(0, ie6xx_wdt_data.sch_wdtba + PV1); in ie6xx_wdt_set_timeout()
183 seq_printf(s, "PV1 = 0x%08x\n", in ie6xx_wdt_show()
184 inl(ie6xx_wdt_data.sch_wdtba + PV1)); in ie6xx_wdt_show()
/openbmc/u-boot/board/compal/paz00/
H A Dpaz00.c36 /* For power GPIO PV1 */ in pin_mux_mmc()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra114-pinmux.yaml37 dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
H A Dnvidia,tegra30-pinmux.yaml75 pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4,
H A Dnvidia,tegra124-pinmux.yaml48 dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi278 pv1 {
279 nvidia,pins = "pv1",
H A Dtegra30-apalis-v1.1.dtsi600 pv1 {
601 nvidia,pins = "pv1";
H A Dtegra30-apalis.dtsi599 pv1 {
600 nvidia,pins = "pv1";
H A Dtegra114-roth.dts609 pv1 {
610 nvidia,pins = "pv1";
H A Dtegra114-dalmore.dts583 pv1 {
584 nvidia,pins = "pv1";
H A Dtegra124-nyan-big.dts818 pv1 {
819 nvidia,pins = "pv1";
H A Dtegra124-nyan-blaze.dts820 pv1 {
821 nvidia,pins = "pv1";
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dpinmux.c42 PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dpinmux.c42 PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
/openbmc/linux/drivers/platform/chrome/
H A Dcros_ec_sensorhub_ring.c136 static int cros_ec_sensor_ring_median_cmp(const void *pv1, const void *pv2) in cros_ec_sensor_ring_median_cmp() argument
138 s64 v1 = *(s64 *)pv1; in cros_ec_sensor_ring_median_cmp()
/openbmc/u-boot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h299 DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c42 PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
/openbmc/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h357 DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/arch/arm/dts/
H A Dtegra124-nyan-big.dts863 pv1 {
864 nvidia,pins = "pv1";
/openbmc/linux/include/media/drv-intf/
H A Dsaa7146.h190 #define PV1 0x0000000008 macro
/openbmc/u-boot/board/nvidia/nyan-big/
H A Dpinmux-config-nyan-big.h204 PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Dpinmux-config-apalis-tk1.h189 PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/nvidia/jetson-tk1/
H A Dpinmux-config-jetson-tk1.h208 PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/cei/cei-tk1-som/
H A Dpinmux-config-cei-tk1-som.h200 PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
/openbmc/u-boot/board/nvidia/venice2/
H A Dpinmux-config-venice2.h215 PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),

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