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/openbmc/u-boot/arch/arm/dts/
H A Dthunderx-88xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Cavium Thunder DTS file - Thunder SoC description
10 compatible = "cavium,thunder-88xx";
11 interrupt-parent = <&gic0>;
12 #address-cells = <2>;
13 #size-cells = <2>;
15 psci {
16 compatible = "arm,psci-0.2";
21 #address-cells = <2>;
22 #size-cells = <0>;
[all …]
H A Dfsl-imx8-ca53.dtsi17 #address-cells = <2>;
18 #size-cells = <0>;
20 idle-states {
21 entry-method = "psci";
23 CPU_SLEEP: cpu-sleep {
24 compatible = "arm,idle-state";
25 local-timer-stop;
26 arm,psci-suspend-param = <0x0000000>;
27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
[all …]
H A Dfsl-imx8-ca35.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8qxp-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <0>;
14 /* We have 1 clusters having 4 Cortex-A35 cores */
15 A35_0: cpu@0 {
17 compatible = "arm,cortex-a35";
18 reg = <0x0 0x0>;
19 enable-method = "psci";
[all …]
H A Dhi6220.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 psci {
17 compatible = "arm,psci-0.2";
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dsun50i-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <sunxi-h3-h5.dtsi>
47 #address-cells = <1>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0>;
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
[all …]
H A Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
47 compatible = "arm,cortex-a53", "arm,armv8";
48 reg = <0x0 0x100>;
49 enable-method = "psci";
50 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a53", "arm,armv8";
57 reg = <0x0 0x101>;
[all …]
H A Darmada-ap806-quad.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include "armada-ap806.dtsi"
51 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a72", "arm,armv8";
60 reg = <0x000>;
61 enable-method = "psci";
65 compatible = "arm,cortex-a72", "arm,armv8";
66 reg = <0x001>;
[all …]
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
36 cpu0: cpu@0 {
37 compatible = "arm,cortex-a53", "arm,armv8";
38 reg = <0x000>;
40 enable-method = "psci";
[all …]
/openbmc/qemu/linux-headers/linux/
H A Dpsci.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * ARM Power State and Coordination Interface (PSCI) header
5 * This header holds common PSCI defines and macros shared
16 * PSCI v0.1 interface
18 * The PSCI v0.1 function numbers are implementation defined.
20 * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
22 * to PSCI v0.1.
25 /* PSCI v0.2 interface */
26 #define PSCI_0_2_FN_BASE 0x84000000
28 #define PSCI_0_2_64BIT 0x40000000
[all …]
/openbmc/u-boot/include/linux/
H A Dpsci.h2 * ARM Power State and Coordination Interface (PSCI) header
4 * This header holds common PSCI defines and macros shared
15 * PSCI v0.1 interface
17 * The PSCI v0.1 function numbers are implementation defined.
19 * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
21 * to PSCI v0.1.
24 /* PSCI v0.2 interface */
25 #define PSCI_0_2_FN_BASE 0x84000000
27 #define PSCI_0_2_64BIT 0x40000000
32 #define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
[all …]
/openbmc/u-boot/drivers/firmware/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on drivers/firmware/psci.c from Linux:
14 #include <linux/arm-smccc.h>
17 #include <linux/psci.h>
19 #define DRIVER_NAME "psci"
39 arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); in invoke_psci_fn()
41 arm_smccc_hvc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); in invoke_psci_fn()
49 /* No SYSTEM_RESET support for PSCI 0.1 */ in psci_bind()
50 if (device_is_compatible(dev, "arm,psci-0.2") || in psci_bind()
51 device_is_compatible(dev, "arm,psci-1.0")) { in psci_bind()
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0043-firmware-psci-Fix-bind_smccc_features-psci-check.patch4 Subject: [PATCH] firmware: psci: Fix bind_smccc_features psci check
6 Message-ID: <20240304144242.11666-2-o451686892@gmail.com> (raw)
7 In-Reply-To: <20240304144242.11666-1-o451686892@gmail.com>
9 According to PSCI specification DEN0022F, PSCI_FEATURES is used to check
12 Signed-off-by: Weizhao Ouyang <o451686892@gmail.com>
13 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
14 Upstream-Status: Submitted [https://lore.kernel.org/all/20240304144242.11666-2-o451686892@gmail.com…
15 ---
16 drivers/firmware/psci.c | 5 ++++-
17 include/linux/arm-smccc.h | 6 ++++++
[all …]
H A D0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch8 Upstream-Status: Submitted [https://lore.kernel.org/all/20240612100421.47938-1-harsimransingh.tunga…
9 Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
10 ---
11 arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++
12 arch/arm/dts/corstone1000.dtsi | 2 +-
13 2 files changed, 26 insertions(+), 1 deletion(-)
15 diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
17 --- a/arch/arm/dts/corstone1000-fvp.dts
18 +++ b/arch/arm/dts/corstone1000-fvp.dts
19 @@ -49,3 +49,28 @@
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dpsci-dt.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/psci.h>
21 unsigned int psci_ver = 0; in fdt_psci()
25 if (nodeoff < 0) { in fdt_psci()
30 /* add 'enable-method = "psci"' to each cpu node */ in fdt_psci()
32 tmp >= 0; in fdt_psci()
42 if (strcmp(prop->data, "cpu")) in fdt_psci()
50 fdt_setprop_string(fdt, tmp, "enable-method", "psci"); in fdt_psci()
53 nodeoff = fdt_path_offset(fdt, "/psci"); in fdt_psci()
54 if (nodeoff >= 0) in fdt_psci()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A DKconfig15 bool "Enable multiple CPUs to enter into U-Boot"
21 CPUECTLR_EL1.SMPEN bit before U-Boot.
36 bool "Support spin-table enable method"
39 Say Y here to support "spin-table" enable method for booting Linux.
42 - Specify enable-method = "spin-table" in each CPU node in the
44 - Bring secondary CPUs into U-Boot proper in a board specific
49 U-Boot automatically does:
50 - Set "cpu-release-addr" property of each CPU node
52 - Reserve the code for the spin-table and the release address
65 - Address of secure firmware.
[all …]
H A Dpsci.S1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
10 #include <asm/psci.h>
12 /* Default PSCI function, return -1, Not Implemented */
20 /* PSCI function and ID table definition*/
27 /* 32 bits PSCI default functions */
71 PSCI_TABLE(0, 0)
73 /* 64 bits PSCI default functions */
97 PSCI_TABLE(0, 0)
100 /* PSCI call is Fast Call(atomic), so mask DAIF */
[all …]
H A Dcpu-dt.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/psci.h>
15 * If the PSCI in SEC Firmware didn't work, avoid to update the in psci_update_dt()
16 * device node of PSCI. But still return 0 instead of an error in psci_update_dt()
17 * number to support detecting PSCI dynamically and then switching in psci_update_dt()
18 * the SMP boot method between PSCI and spin-table. in psci_update_dt()
21 return 0; in psci_update_dt()
27 __secure_end - __secure_start); in psci_update_dt()
30 return 0; in psci_update_dt()
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1043a_psci.S1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
10 #include <asm/psci.h>
16 ldr w0, =0x00010000 /* PSCI v1.0 */
/openbmc/qemu/target/arm/tcg/
H A Dpsci.c2 * Copyright (C) 2014 - Linaro
21 #include "exec/helper-proto.h"
22 #include "kvm-consts.h"
23 #include "qemu/main-loop.h"
26 #include "arm-powerctl.h"
32 * Return true if the exception type matches the configured PSCI conduit. in arm_is_psci_call()
34 * whether we should treat it as a PSCI call or with the architecturally in arm_is_psci_call()
41 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) { in arm_is_psci_call()
46 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { in arm_is_psci_call()
61 * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b), in arm_handle_psci_call()
[all …]
/openbmc/u-boot/board/ucRobotics/bubblegum_96/
H A Dbubblegum_96.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Bubblegum-96 Boards Support
8 #include <linux/arm-smccc.h>
9 #include <linux/psci.h>
12 #include <asm/mach-types.h>
13 #include <asm/psci.h>
18 * dram_init - sets uboots idea of sdram size
22 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; in dram_init()
23 return 0; in dram_init()
29 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
[all …]
/openbmc/qemu/hw/arm/
H A Dboot.c4 * Copyright (c) 2006-2007 CodeSourcery.
12 #include "qemu/error-report.h"
16 #include "hw/arm/linux-boot-if.h"
30 #include "qemu/config-file.h"
39 #define KERNEL_ARGS_ADDR 0x100
40 #define KERNEL_NOLOAD_ADDR 0x02000000
41 #define KERNEL_LOAD_ADDR 0x00010000
42 #define KERNEL64_LOAD_ADDR 0x00080000
59 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { in arm_boot_address_space()
69 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dpsci.h2 * Copyright (C) 2013 - ARM Ltd
21 #define ARM_PSCI_VER_1_0 (0x00010000)
22 #define ARM_PSCI_VER_0_2 (0x00000002)
24 /* PSCI 0.1 interface */
25 #define ARM_PSCI_FN_BASE 0x95c1ba5e
28 #define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
33 #define ARM_PSCI_RET_SUCCESS 0
34 #define ARM_PSCI_RET_NI (-1)
35 #define ARM_PSCI_RET_INVAL (-2)
36 #define ARM_PSCI_RET_DENIED (-3)
[all …]
/openbmc/qemu/target/arm/
H A Dkvm-consts.h8 * KVM headers. If CONFIG_KVM is set, we do a compile-time check
12 * See the COPYING file in the top-level directory.
20 #include <linux/psci.h>
26 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
30 #define CP_REG_SIZE_MASK 0x00f0000000000000ULL
31 #define CP_REG_SIZE_U32 0x0020000000000000ULL
32 #define CP_REG_SIZE_U64 0x0030000000000000ULL
33 #define CP_REG_ARM 0x4000000000000000ULL
34 #define CP_REG_ARCH_MASK 0xff00000000000000ULL
43 #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
[all …]
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DKconfig11 default "fsl-layerscape"
17 bool "Enable secure address for PSCI image"
21 PSCI image can be re-located to secure RAM.
28 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
29 default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
34 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
35 default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
/openbmc/u-boot/drivers/sysreset/
H A Dsysreset_psci.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/psci.h>
25 return -ENOSYS; in psci_sysreset_request()
28 invoke_psci_fn(function_id, 0, 0, 0); in psci_sysreset_request()
30 return -EINPROGRESS; in psci_sysreset_request()
38 .name = "psci-sysreset",

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