| /openbmc/qemu/hw/misc/ |
| H A D | zynq_slcr.c | 198 Clock *ps_clk; member
276 static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk) in zynq_slcr_compute_clocks_internal() argument
278 uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
279 uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
280 uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
298 uint64_t ps_clk = clock_get(s->ps_clk); in zynq_slcr_compute_clocks() local
302 ps_clk = 0; in zynq_slcr_compute_clocks()
305 zynq_slcr_compute_clocks_internal(s, ps_clk); in zynq_slcr_compute_clocks()
436 /* will compute output clocks according to ps_clk and registers */ in zynq_slcr_reset_exit()
437 zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); in zynq_slcr_reset_exit()
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| /openbmc/linux/drivers/clk/zynq/ |
| H A D | clkc.c | 61 static struct clk *ps_clk; variable
80 "ps_clk"};
82 "ps_clk"};
84 "ps_clk"};
249 /* ps_clk */ in zynq_clk_setup()
252 pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); in zynq_clk_setup()
255 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); in zynq_clk_setup()
258 clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, in zynq_clk_setup()
264 clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, in zynq_clk_setup()
270 clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, in zynq_clk_setup()
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| /openbmc/qemu/hw/arm/ |
| H A D | xilinx_zynq.c | 93 Clock *ps_clk; member
251 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); in zynq_init()
252 object_property_add_child(OBJECT(zynq_machine), "ps_clk", in zynq_init()
253 OBJECT(zynq_machine->ps_clk)); in zynq_init()
254 object_unref(OBJECT(zynq_machine->ps_clk)); in zynq_init()
255 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); in zynq_init()
259 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); in zynq_init()
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | mxicy,mx25f0a-spi.yaml | 39 - const: ps_clk
62 clock-names = "send_clk", "send_dly_clk", "ps_clk";
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | mxic_nand.c | 174 struct clk *ps_clk; member
188 ret = clk_prepare_enable(nfc->ps_clk); in mxic_nfc_clk_enable()
205 clk_disable_unprepare(nfc->ps_clk); in mxic_nfc_clk_enable()
214 clk_disable_unprepare(nfc->ps_clk); in mxic_nfc_clk_disable()
500 nfc->ps_clk = devm_clk_get(&pdev->dev, "ps"); in mxic_nfc_probe()
501 if (IS_ERR(nfc->ps_clk)) in mxic_nfc_probe()
502 return PTR_ERR(nfc->ps_clk); in mxic_nfc_probe()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | mxicy,nand-ecc-engine.yaml | 39 clock-names = "send_clk", "send_dly_clk", "ps_clk";
62 clock-names = "send_clk", "send_dly_clk", "ps_clk";
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-mxic.c | 173 struct clk *ps_clk; member
720 clk_disable_unprepare(mxic->ps_clk); in mxic_spi_runtime_suspend()
731 ret = clk_prepare_enable(mxic->ps_clk); in mxic_spi_runtime_resume()
763 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); in mxic_spi_probe()
764 if (IS_ERR(mxic->ps_clk)) in mxic_spi_probe()
765 return PTR_ERR(mxic->ps_clk); in mxic_spi_probe()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | zynq-7000.txt | 18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun6i-a31.c | 619 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
939 &ps_clk.common,
1127 [CLK_PS] = &ps_clk.common.hw,
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