Searched full:pllp_out4 (Results 1 – 19 of 19) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | nvidia,tegra20-pinmux.yaml | 64 pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
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/openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
H A D | pinmux.c | 290 PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra20-trimslice.dts | 66 nvidia,function = "pllp_out4";
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H A D | tegra20-tamonten.dtsi | 61 nvidia,function = "pllp_out4";
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H A D | tegra20-paz00.dts | 74 nvidia,function = "pllp_out4";
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H A D | tegra20-ventana.dts | 77 nvidia,function = "pllp_out4";
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H A D | tegra20-colibri.dtsi | 178 nvidia,function = "pllp_out4";
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H A D | tegra20-harmony.dts | 75 nvidia,function = "pllp_out4";
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H A D | tegra20-seaboard.dts | 75 nvidia,function = "pllp_out4";
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H A D | tegra20-asus-tf101.dts | 132 nvidia,function = "pllp_out4";
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H A D | tegra20-acer-a500-picasso.dts | 118 nvidia,function = "pllp_out4";
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/openbmc/u-boot/arch/arm/dts/ |
H A D | tegra20-tamonten.dtsi | 50 nvidia,function = "pllp_out4";
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H A D | tegra20-paz00.dts | 90 nvidia,function = "pllp_out4";
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H A D | tegra20-ventana.dts | 96 nvidia,function = "pllp_out4";
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H A D | tegra20-harmony.dts | 96 nvidia,function = "pllp_out4";
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H A D | tegra20-seaboard.dts | 106 nvidia,function = "pllp_out4";
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/openbmc/u-boot/arch/arm/mach-tegra/ |
H A D | clock.c | 754 * and then switch back to PLLP_OUT4, which has an appropriate divider in tegra30_set_up_pllp()
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/openbmc/linux/drivers/pinctrl/tegra/ |
H A D | pinctrl-tegra20.c | 1929 FUNCTION(pllp_out4), 2052 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
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/openbmc/u-boot/drivers/usb/host/ |
H A D | ehci-tegra.c | 593 /* set up ULPI reference clock on pllp_out4 */ in init_ulpi_usb_controller()
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