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Searched full:pllc1 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-davinci/
H A DKconfig124 hex "PLLC1 PLL Post-Divider"
127 Value written to PLLC1 PLL Post-Divider Control Register
130 hex "PLLC1 Divider 2"
133 Value written to PLLC1 Divider 1 register
136 hex "PLLC1 Divider 2"
139 Value written to PLLC1 Divider 2 register
142 hex "PLLC1 Divider 3"
145 Value written to PLLC1 Divider 3 register
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h95 u32 pllc1; member
122 u32 pllc1; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c75 writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); in cm_basic_init()
97 writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); in cm_basic_init()
281 clock /= (readl(&clock_manager_base->main_pll.pllc1) & in cm_get_l3_main_clk_hz()
287 clock /= (readl(&clock_manager_base->per_pll.pllc1) & in cm_get_l3_main_clk_hz()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-clocks.yaml107 - const: pllc1
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
/openbmc/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c101 } else if (!strcmp(name, "pllc1")) { in r8a7740_cpg_register_clock()
123 parent_name = "pllc1"; in r8a7740_cpg_register_clock()
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h431 * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi484 clock-output-names = "system", "pllc0", "pllc1",