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Searched full:pllc0 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-davinci/
H A DKconfig76 int "PLLC0 PLL Post-Divider"
79 Value written to PLLC0 PLL Post-Divider Control Register
82 hex "PLLC0 Divider 1"
85 Value written to PLLC0 Divider 1 register
88 hex "PLLC0 Divider 2"
91 Value written to PLLC0 Divider 2 register
94 hex "PLLC0 Divider 3"
97 Value written to PLLC0 Divider 3 register
100 hex "PLLC0 Divider 4"
103 Value written to PLLC0 Divider 4 register
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h94 u32 pllc0; member
121 u32 pllc0; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c74 writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); in cm_basic_init()
96 writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); in cm_basic_init()
244 clock /= (readl(&clock_manager_base->main_pll.pllc0) & in cm_get_mpu_clk_hz()
250 clock /= (readl(&clock_manager_base->per_pll.pllc0) & in cm_get_mpu_clk_hz()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-clocks.yaml106 - const: pllc0
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
/openbmc/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c92 } else if (!strcmp(name, "pllc0")) { in r8a7740_cpg_register_clock()
93 /* PLLC0/1 are configurable multiplier clocks. Register them as in r8a7740_cpg_register_clock()
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h431 * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi484 clock-output-names = "system", "pllc0", "pllc1",