| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intel-i915-hwmon | 13 Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
17 exceeds this limit. A read value of 0 means that the PL1
35 Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
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| H A D | sysfs-platform-asus-wmi | 135 Set the Package Power Target total of CPU: PL1 on Intel, SPL on AMD.
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| /openbmc/qemu/target/hppa/ |
| H A D | trace-events | 11 …, int access_id, int u, int pl2, int pl1, int type, int b, int d, int t) "env=%p ent=%p access_id=…
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| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | timer.c | 67 /* Set PL1 Physical Timer Ctrl */ in timer_init()
71 /* Set PL1 Physical Comp Value */ in timer_init()
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| H A D | cpu.c | 387 /* Disable PL1 Physical Timer */ in arch_preboot_os()
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| /openbmc/linux/arch/arm/boot/dts/allwinner/ |
| H A D | sunxi-bananapi-m2-plus-v1.2.dtsi | 22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| H A D | sun8i-h2-plus-bananapi-m2-zero.dts | 71 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| H A D | sun8i-a23-a33.dtsi | 823 pins = "PL0", "PL1";
829 pins = "PL0", "PL1";
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| /openbmc/qemu/tests/tcg/arm/system/ |
| H A D | boot.S | 126 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RO @ PL1 */
136 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RW @ PL1 */
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | booting.rst | 222 the HYP mode configuration in addition to the ordinary PL1 (privileged
224 hypervisor must be disabled, and PL1 access must be granted for all
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_hwmon.c | 359 * HW allows arbitrary PL1 limits to be set but silently clamps these values to
361 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
371 /* Check if PL1 limit is disabled */ in hwm_power_max_read()
431 /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ in hwm_power_max_write()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_zynqmp.c | 142 pl0, pl1, pl2, pl3, enumerator
168 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
230 case pl1: in zynqmp_clk_get_register()
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| /openbmc/qemu/target/arm/ |
| H A D | cpregs.h | 265 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
266 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
269 * in higher privilege levels too. Since "Secure PL1" also follows this rule
270 * (ie anything visible in PL2 is visible in S-PL1, some things are only
271 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
315 * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
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| H A D | cpu.h | 2788 * + NonSecure PL1 & 0 stage 1
2789 * + NonSecure PL1 & 0 stage 2
2791 * + Secure PL1 & 0
2792 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2826 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
2827 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
2828 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
2833 * EL3 (aka AArch32 S PL1 PL1&0)
2834 * AArch32 S PL0 PL1&0 (we call this EL30_0)
2835 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN)
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| /openbmc/u-boot/board/freescale/s32v234evb/ |
| H A D | s32v234evb.c | 126 /* PL1 pad: uSDHC DAT6 */ in board_mmc_init()
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra210-pinmux.yaml | 56 pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | head-nommu.S | 291 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
303 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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| H A D | hyp-stub.S | 146 @ make CNTP_* and CNTPCT accessible from PL1
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynqmp-clk-ccf.dtsi | 96 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
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| H A D | sun50i-h6.dtsi | 270 pins = "PL0", "PL1";
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| /openbmc/linux/tools/arch/arm/include/uapi/asm/ |
| H A D | kvm.h | 179 /* PL1 Physical Timer Registers */
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| /openbmc/qemu/linux-headers/asm-arm/ |
| H A D | kvm.h | 179 /* PL1 Physical Timer Registers */
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| /openbmc/linux/arch/arm64/boot/dts/allwinner/ |
| H A D | sun50i-h616.dtsi | 699 pins = "PL0", "PL1";
704 pins = "PL0", "PL1";
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| H A D | sun50i-a100.dtsi | 319 pins = "PL0", "PL1";
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | pinmux.c | 186 PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
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