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/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_me_regs.h112 /* DEC200 Peripheral Control Register */
114 /* 2D-ACE Peripheral Control Register */
116 /* ENET Peripheral Control Register */
118 /* DMACHMUX0 Peripheral Control Register */
120 /* CSI0 Peripheral Control Register */
122 /* MMDC0 Peripheral Control Register */
124 /* FRAY Peripheral Control Register */
126 /* PIT0 Peripheral Control Register */
128 /* FlexTIMER0 Peripheral Control Register */
130 /* SARADC0 Peripheral Control Register */
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dpinmux.c13 static void exynos5_uart_config(int peripheral) in exynos5_uart_config() argument
17 switch (peripheral) { in exynos5_uart_config()
35 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5_uart_config()
44 static void exynos5420_uart_config(int peripheral) in exynos5420_uart_config() argument
48 switch (peripheral) { in exynos5420_uart_config()
66 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5420_uart_config()
76 static int exynos5_mmc_config(int peripheral, int flags) in exynos5_mmc_config() argument
80 switch (peripheral) { in exynos5_mmc_config()
100 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5_mmc_config()
105 peripheral); in exynos5_mmc_config()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l56-sdw.c26 static int cs35l56_sdw_read_one(struct sdw_slave *peripheral, unsigned int reg, void *buf) in cs35l56_sdw_read_one() argument
30 ret = sdw_nread_no_pm(peripheral, reg, 4, (u8 *)buf); in cs35l56_sdw_read_one()
32 dev_err(&peripheral->dev, "Read failed @%#x:%d\n", reg, ret); in cs35l56_sdw_read_one()
45 struct sdw_slave *peripheral = context; in cs35l56_sdw_read() local
54 return cs35l56_sdw_read_one(peripheral, reg, val_buf); in cs35l56_sdw_read()
61 ret = sdw_nread_no_pm(peripheral, reg, bytes, buf8); in cs35l56_sdw_read()
63 dev_err(&peripheral->dev, "Read failed @%#x..%#x:%d\n", in cs35l56_sdw_read()
86 static int cs35l56_sdw_write_one(struct sdw_slave *peripheral, unsigned int reg, const void *buf) in cs35l56_sdw_write_one() argument
91 ret = sdw_nwrite_no_pm(peripheral, reg, 4, (u8 *)&val_le); in cs35l56_sdw_write_one()
93 dev_err(&peripheral->dev, "Write failed @%#x:%d\n", reg, ret); in cs35l56_sdw_write_one()
[all …]
H A Dcs42l42-sdw.c203 static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match) in cs42l42_sdw_poll_status() argument
210 false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); in cs42l42_sdw_poll_status()
215 dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n", in cs42l42_sdw_poll_status()
223 struct sdw_slave *peripheral = context; in cs42l42_sdw_read() local
229 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0); in cs42l42_sdw_read()
233 ret = sdw_read_no_pm(peripheral, reg); in cs42l42_sdw_read()
235 dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret); in cs42l42_sdw_read()
240 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); in cs42l42_sdw_read()
242 dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret); in cs42l42_sdw_read()
254 ret = cs42l42_sdw_poll_status(peripheral, in cs42l42_sdw_read()
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h114 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
117 * @param periph_id peripheral to reset
123 * Put a peripheral into or out of reset.
125 * @param periph_id peripheral to reset
150 * Set the source for a peripheral clock. This plus the divisor sets the
152 * source parameter as it changes for each peripheral.
157 * @param periph_id peripheral to adjust
166 * @param periph_id peripheral to adjust
174 * Set the source and divisor for a peripheral clock. This sets the
176 * source parameter as it changes for each peripheral.
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/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
27 translated depends on the connected peripheral. Also there is a
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
40 field as required by peripheral, educate generic timing routine to
42 Then there may be cases where peripheral datasheet doesn't mention
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc37 - High-speed peripheral interfaces
40 - Additional peripheral interfaces
43 - Quad Serial Peripheral Interface (QSPI) Controller
44 - Serial peripheral interface (SPI) controller
55 and networks, peripheral interfaces required for
86 and peripheral bus interfaces required for networking, telecom/datacom,
110 - High-speed peripheral interfaces
112 - Additional peripheral interfaces
116 - Serial peripheral interface (SPI) controller
117 - Quad Serial Peripheral Interface (QSPI) Controller
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dmipi-dsi-bus.txt15 The following assumes that only a single peripheral is connected to a DSI
34 conjunction with another DSI host to drive the same peripheral. Hardware
39 DSI peripheral
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
58 that the peripheral responds to.
59 - If the virtual channels that a peripheral responds to are consecutive, the
79 connected to this peripheral. Each DSI host's output endpoint can be linked to
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
89 - (4) is an example of a peripheral on a I2C control bus connected to a
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dpistachio-clock.txt4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals. It also contains miscellaneous peripheral
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/openbmc/u-boot/include/
H A Dstm32_rcc.h64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
68 u32 apb1rstr; /* RCC APB1 peripheral reset */
69 u32 apb2rstr; /* RCC APB2 peripheral reset */
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
72 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
73 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
75 u32 apb1enr; /* RCC APB1 peripheral clock enable */
76 u32 apb2enr; /* RCC APB2 peripheral clock enable */
/openbmc/linux/drivers/usb/gadget/udc/
H A DKconfig4 # (a) a peripheral controller, and
18 # USB Peripheral Controller Support
27 menu "USB Peripheral Controller"
47 tristate "LPC32XX USB Peripheral Controller"
81 tristate "Broadcom BCM63xx Peripheral Controller"
92 tristate "Freescale Highspeed USB DR Peripheral Controller"
106 tristate "Faraday FUSB300 USB Peripheral Controller"
112 tristate "Aeroflex Gaisler GRUSBDC USB Peripheral Controller Driver"
159 tristate "Renesas R8A66597 USB Peripheral Controller"
162 R8A66597 is a discrete USB host and peripheral controller chip that
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/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dpinmux.h28 * Configures the pinmux for a particular peripheral.
32 * etc. This function will configure the peripheral pinmux along with
35 * @param peripheral peripheral to be configured
37 * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
39 int exynos_pinmux_config(int peripheral, int flags);
42 * Decode the peripheral id using the interrpt numbers.
46 * @return peripheral id if ok, PERIPH_ID_NONE on error
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dpinmux.h31 * Configures the pinmux for a particular peripheral.
35 * etc. This function will configure the peripheral pinmux along with
38 * @param peripheral peripheral to be configured
40 * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
42 int exynos_pinmux_config(int peripheral, int flags);
45 * Decode the peripheral id using the interrpt numbers.
49 * @return peripheral id if ok, PERIPH_ID_NONE on error
/openbmc/linux/drivers/rtc/
H A Drtc-meson.c66 struct regmap *peripheral; /* peripheral registers */ member
71 .name = "peripheral-registers",
84 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0); in meson_rtc_sclk_pulse()
86 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, in meson_rtc_sclk_pulse()
92 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, in meson_rtc_send_bit()
110 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0); in meson_rtc_set_dir()
111 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0); in meson_rtc_set_dir()
113 regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0); in meson_rtc_set_dir()
125 regmap_read(rtc->peripheral, RTC_ADDR1, &tmp); in meson_rtc_get_data()
139 regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0); in meson_rtc_get_bus()
[all …]
/openbmc/linux/drivers/clk/qcom/
H A DKconfig109 Say Y if you want to use peripheral devices such as UART, SPI,
146 Say Y if you want to use peripheral devices such as UART, SPI,
154 Say Y if you want to use peripheral devices such as UART, SPI,
162 Say Y if you want to use peripheral devices such as UART, SPI,
169 Say Y if you want to use peripheral devices such as UART, SPI,
178 Say Y if you want to use peripheral devices such as UART, SPI,
195 Say Y if you want to use peripheral devices such as UART, SPI,
203 Say Y if you want to use peripheral devices such as UART, SPI,
212 Say Y if you want to use peripheral devices such as UART, SPI,
255 Say Y if you want to use peripheral devices such as UART, SPI,
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dimg,pdc-intc.txt27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
35 0-7: Peripheral interrupts
39 flags as follows (only 4 valid for peripheral interrupts):
74 <30 4 /* level */>, /* Peripheral 0 (RTC) */
75 <29 4 /* level */>, /* Peripheral 1 (IR) */
76 <31 4 /* level */>; /* Peripheral 2 (WDT) */
82 * An SoC peripheral that is wired through the PDC.
88 // Interrupt source Peripheral 0
89 interrupts = <0 /* Peripheral 0 (RTC) */
/openbmc/u-boot/arch/arm/cpu/armv8/hisilicon/
H A Dpinmux.c19 static void hi6220_uart_config(int peripheral) in hi6220_uart_config() argument
21 switch (peripheral) { in hi6220_uart_config()
97 debug("%s: invalid peripheral %d", __func__, peripheral); in hi6220_uart_config()
102 static int hi6220_mmc_config(int peripheral) in hi6220_mmc_config() argument
106 switch (peripheral) { in hi6220_mmc_config()
156 debug("%s: invalid peripheral %d", __func__, peripheral); in hi6220_mmc_config()
163 int hi6220_pinmux_config(int peripheral) in hi6220_pinmux_config() argument
165 switch (peripheral) { in hi6220_pinmux_config()
170 hi6220_uart_config(peripheral); in hi6220_pinmux_config()
174 return hi6220_mmc_config(peripheral); in hi6220_pinmux_config()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmc-peripheral-props.yaml4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
38 - $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
/openbmc/u-boot/include/spmi/
H A Dspmi.h10 * @read: read register 'reg' of slave 'usid' and peripheral 'pid'
11 * @write: write register 'reg' of slave 'usid' and peripheral 'pid'
23 * spmi_reg_read() - read a register from specific slave/peripheral
27 * @pid Peripheral ID
34 * spmi_reg_write() - write a register of specific slave/peripheral
38 * @pid Peripheral ID
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-platform-renesas_usb311 - "host" - switching mode from peripheral to host.
12 - "peripheral" - switching mode from host to peripheral.
17 - "peripheral" - The mode is peripheral now.
H A Dsysfs-platform-phy-rcar-gen3-usb211 - "host" - switching mode from peripheral to host.
12 - "peripheral" - switching mode from host to peripheral.
17 - "peripheral" - The mode is peripheral now.
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_mipi_dsi.c242 * @dsi: DSI peripheral device
369 * @dsi: DSI peripheral
391 * @dsi: DSI peripheral
419 * @dsi: DSI peripheral
583 * mipi_dsi_shutdown_peripheral() - sends a Shutdown Peripheral command
584 * @dsi: DSI peripheral device
603 * mipi_dsi_turn_on_peripheral() - sends a Turn On Peripheral command
604 * @dsi: DSI peripheral device
624 * the payload in a long packet transmitted from the peripheral back to the
626 * @dsi: DSI peripheral device
[all …]
/openbmc/linux/include/linux/mfd/
H A Dsta2x11-mfd.h204 #define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
205 #define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
206 #define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
207 #define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
208 #define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
216 #define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
217 #define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
218 #define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
219 #define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
220 #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A DKconfig3 # (a) a peripheral controller, and
20 host (such as a PC) controlling up to 127 peripheral devices.
22 you can't connect a "to-the-host" connector to a peripheral.
24 U-Boot can run in the host, or in the peripheral. In both cases
26 talking to it. Peripheral controllers are often discrete silicon,
33 a USB peripheral device. Configure one hardware driver for your
34 peripheral/device side bus controller, and a "gadget driver" for
35 your peripheral protocol.
96 driver to operate in Peripheral mode. This option requires
179 Creates an Ethernet network device through a USB peripheral
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dsamsung,sysmmu.yaml14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
23 System MMUs are in many to one relation with peripheral devices, i.e. single
24 peripheral device might have multiple System MMUs (usually one for each bus
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
27 defined in device node of the peripheral device.
37 For information on assigning System MMU controller to its peripheral devices,

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