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/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_me_regs.h112 /* DEC200 Peripheral Control Register */
114 /* 2D-ACE Peripheral Control Register */
116 /* ENET Peripheral Control Register */
118 /* DMACHMUX0 Peripheral Control Register */
120 /* CSI0 Peripheral Control Register */
122 /* MMDC0 Peripheral Control Register */
124 /* FRAY Peripheral Control Register */
126 /* PIT0 Peripheral Control Register */
128 /* FlexTIMER0 Peripheral Control Register */
130 /* SARADC0 Peripheral Control Register */
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dpinmux.c13 static void exynos5_uart_config(int peripheral) in exynos5_uart_config() argument
17 switch (peripheral) { in exynos5_uart_config()
35 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5_uart_config()
44 static void exynos5420_uart_config(int peripheral) in exynos5420_uart_config() argument
48 switch (peripheral) { in exynos5420_uart_config()
66 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5420_uart_config()
76 static int exynos5_mmc_config(int peripheral, int flags) in exynos5_mmc_config() argument
80 switch (peripheral) { in exynos5_mmc_config()
100 debug("%s: invalid peripheral %d", __func__, peripheral); in exynos5_mmc_config()
105 peripheral); in exynos5_mmc_config()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h114 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
117 * @param periph_id peripheral to reset
123 * Put a peripheral into or out of reset.
125 * @param periph_id peripheral to reset
150 * Set the source for a peripheral clock. This plus the divisor sets the
152 * source parameter as it changes for each peripheral.
157 * @param periph_id peripheral to adjust
166 * @param periph_id peripheral to adjust
174 * Set the source and divisor for a peripheral clock. This sets the
176 * source parameter as it changes for each peripheral.
[all …]
H A Dfuncmux.h12 * Select a config for a particular peripheral.
14 * Each peripheral can operate through a number of configurations,
17 * pinmux settings to bring the peripheral out on other pins,
22 * @param id Peripheral id
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dpinmux.h28 * Configures the pinmux for a particular peripheral.
32 * etc. This function will configure the peripheral pinmux along with
35 * @param peripheral peripheral to be configured
37 * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
39 int exynos_pinmux_config(int peripheral, int flags);
42 * Decode the peripheral id using the interrpt numbers.
46 * @return peripheral id if ok, PERIPH_ID_NONE on error
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dpinmux.h31 * Configures the pinmux for a particular peripheral.
35 * etc. This function will configure the peripheral pinmux along with
38 * @param peripheral peripheral to be configured
40 * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
42 int exynos_pinmux_config(int peripheral, int flags);
45 * Decode the peripheral id using the interrpt numbers.
49 * @return peripheral id if ok, PERIPH_ID_NONE on error
H A Dclk.h54 * get the clk frequency of the required peripheral
56 * @param peripheral Peripheral id
58 * @return frequency of the peripheral clk
60 unsigned long clock_get_periph_rate(int peripheral);
/openbmc/u-boot/include/
H A Dstm32_rcc.h64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
68 u32 apb1rstr; /* RCC APB1 peripheral reset */
69 u32 apb2rstr; /* RCC APB2 peripheral reset */
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
72 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
73 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
75 u32 apb1enr; /* RCC APB1 peripheral clock enable */
76 u32 apb2enr; /* RCC APB2 peripheral clock enable */
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc37 - High-speed peripheral interfaces
40 - Additional peripheral interfaces
43 - Quad Serial Peripheral Interface (QSPI) Controller
44 - Serial peripheral interface (SPI) controller
55 and networks, peripheral interfaces required for
86 and peripheral bus interfaces required for networking, telecom/datacom,
110 - High-speed peripheral interfaces
112 - Additional peripheral interfaces
116 - Serial peripheral interface (SPI) controller
117 - Quad Serial Peripheral Interface (QSPI) Controller
[all …]
/openbmc/u-boot/include/spmi/
H A Dspmi.h10 * @read: read register 'reg' of slave 'usid' and peripheral 'pid'
11 * @write: write register 'reg' of slave 'usid' and peripheral 'pid'
23 * spmi_reg_read() - read a register from specific slave/peripheral
27 * @pid Peripheral ID
34 * spmi_reg_write() - write a register of specific slave/peripheral
38 * @pid Peripheral ID
/openbmc/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dpinmux.h71 * Configures the pinmux for a particular peripheral.
73 * This function will configure the peripheral pinmux along with
76 * @param peripheral peripheral to be configured
77 * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
79 int hi6220_pinmux_config(int peripheral);
/openbmc/u-boot/arch/arm/cpu/armv8/hisilicon/
H A Dpinmux.c19 static void hi6220_uart_config(int peripheral) in hi6220_uart_config() argument
21 switch (peripheral) { in hi6220_uart_config()
97 debug("%s: invalid peripheral %d", __func__, peripheral); in hi6220_uart_config()
102 static int hi6220_mmc_config(int peripheral) in hi6220_mmc_config() argument
106 switch (peripheral) { in hi6220_mmc_config()
156 debug("%s: invalid peripheral %d", __func__, peripheral); in hi6220_mmc_config()
163 int hi6220_pinmux_config(int peripheral) in hi6220_pinmux_config() argument
165 switch (peripheral) { in hi6220_pinmux_config()
170 hi6220_uart_config(peripheral); in hi6220_pinmux_config()
174 return hi6220_mmc_config(peripheral); in hi6220_pinmux_config()
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A DKconfig3 # (a) a peripheral controller, and
20 host (such as a PC) controlling up to 127 peripheral devices.
22 you can't connect a "to-the-host" connector to a peripheral.
24 U-Boot can run in the host, or in the peripheral. In both cases
26 talking to it. Peripheral controllers are often discrete silicon,
33 a USB peripheral device. Configure one hardware driver for your
34 peripheral/device side bus controller, and a "gadget driver" for
35 your peripheral protocol.
96 driver to operate in Peripheral mode. This option requires
179 Creates an Ethernet network device through a USB peripheral
[all …]
/openbmc/qemu/tests/qemu-iotests/tests/
H A Dqom-set-drive57 log(self.vm.qmp('qom-get', path='/machine/peripheral/iot',
59 log(self.vm.qmp('qom-set', path='/machine/peripheral/iot',
61 log(self.vm.qmp('qom-get', path='/machine/peripheral/iot',
64 log(self.vm.qmp('qom-get', path='/machine/peripheral/no-iot',
66 log(self.vm.qmp('qom-set', path='/machine/peripheral/no-iot',
68 log(self.vm.qmp('qom-get', path='/machine/peripheral/no-iot',
/openbmc/qemu/tests/qemu-iotests/
H A D186.out9 /machine/peripheral-anon/device[1]: [not inserted]
10 Attached to: /machine/peripheral-anon/device[N]
25 /machine/peripheral-anon/device[1]: [not inserted]
26 Attached to: /machine/peripheral-anon/device[N]
41 /machine/peripheral-anon/device[1]: [not inserted]
42 Attached to: /machine/peripheral-anon/device[N]
61 Attached to: /machine/peripheral-anon/device[N]
77 Attached to: /machine/peripheral-anon/device[N]
93 Attached to: /machine/peripheral-anon/device[N]/virtio-backend
101 Attached to: /machine/peripheral/qdev_id/virtio-backend
[all …]
/openbmc/qemu/include/hw/nvram/
H A Dnrf51_nvm.h8 * + sysbus MMIO regions 0: NVMC peripheral registers
9 * + sysbus MMIO regions 1: FICR peripheral registers
10 * + sysbus MMIO regions 2: UICR peripheral registers
13 * Accuracy of the peripheral model:
/openbmc/qemu/include/hw/ssi/
H A Dssi.h5 * implementation has a single peripheral on a "bus".
9 * It is assumed that master and peripheral are both using the same transfer
21 #define TYPE_SSI_PERIPHERAL "ssi-peripheral"
84 * ssi_realize_and_unref: realize and unref an SSI peripheral
85 * @dev: SSI peripheral to realize
99 * If you are embedding the SSI peripheral into another QOM device and
/openbmc/u-boot/arch/arm/mach-imx/
H A Drdc-sema.c13 * Check if the RDC Semaphore is required for this peripheral.
23 * Intial value or this peripheral is assigned to only one domain in imx_rdc_check_sema_required()
32 * Check the peripheral read / write access permission on Domain [dom_id].
47 * Lock up the RDC semaphore for this peripheral if semaphore is required.
76 * Unlock the RDC semaphore for this peripheral if main CPU is the
104 * Setup RDC setting for one peripheral
/openbmc/u-boot/arch/arm/mach-zynq/
H A Dslcr.c24 * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
26 * @peri_name: Name of the peripheral for checking MIO status
27 * @get_pins: Pointer to array of get pin for this peripheral
28 * @num_pins: Number of pins for this peripheral
171 * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
173 * @periph: Name of the peripheral
/openbmc/qemu/docs/interop/
H A Dvirtio-balloon-stats.rst67 which generates ``/machine/peripheral-anon/device[1]`` as the QOM path for
73 "arguments": { "path": "/machine/peripheral-anon/device[1]",
81 "arguments": { "path": "/machine/peripheral-anon/device[1]",
89 "arguments": { "path": "/machine/peripheral-anon/device[1]",
108 "arguments": { "path": "/machine/peripheral-anon/device[1]",
/openbmc/u-boot/drivers/usb/
H A DKconfig16 Say Y here if your device has an USB port, either host, peripheral or
26 If your system has a device-side USB port, used in the peripheral
59 Enable driver model for USB Gadget (Peripheral
67 (Peripheral mode)
/openbmc/u-boot/doc/
H A DREADME.arm-caches20 Memory to Peripheral DMA:
24 Peripheral to Memory DMA:
37 - Any buffer that is invalidated(that is, typically the peripheral to
/openbmc/qemu/include/hw/misc/
H A Dnrf51_rng.h11 * + Named GPIO output "irq": Interrupt line of the peripheral. Must be
12 * connected to the associated peripheral interrupt line of the NVIC.
20 * Accuracy of the peripheral model:
/openbmc/u-boot/doc/device-tree-bindings/pmic/
H A Dpm8916.txt8 - #address-cells: 0x1 (peripheral ID)
9 - #size-cells: 0x1 (size of peripheral register space)
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Ddma.h43 * DMAC_DEST_PERIP: Macro for loading destination peripheral
44 * DMAC_SRC_PERIP: Macro for loading source peripheral
53 * (source and destination peripheral ID numbers).

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