| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
|
| /openbmc/linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
8 memory devices like
14 * Pseudo-SRAM devices
23 GPMC has certain timings that has to be programmed for proper
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
26 be translated to the form gpmc can understand. The way it has to be
27 translated depends on the connected peripheral. Also there is a
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
14 and there can be multiple peripherals attached to a controller. All
20 - Marek Vasut <marex@denx.de>
26 bank-width:
[all …]
|
| /openbmc/qemu/docs/interop/ |
| H A D | virtio-balloon-stats.rst | 1 Virtio balloon memory statistics
4 The virtio balloon driver supports guest memory statistics reporting. These
5 statistics are available to QEMU users as QOM (QEMU Object Model) device
8 Before querying the available stats, clients first have to enable polling.
9 This is done by writing a time interval value (in seconds) to the
10 guest-stats-polling-interval property. This value can be:
14 enabled, the polling time interval is changed to the new value
20 Once polling is enabled, the virtio-balloon device in QEMU will start
24 To retrieve those stats, clients have to query the guest-stats property,
29 its value will be -1. Currently, the following stats are supported:
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
23 System MMUs are in many to one relation with peripheral devices, i.e. single
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
5 - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
6 "microchip,sama7g5-dma" or
7 "microchip,sam9x7-dma", "atmel,sama5d4-dma".
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain DMA interrupt.
10 - #dma-cells: Must be <1>, used to represent the number of integer cells in
12 - The 1st cell specifies the channel configuration register:
13 - bit 13: SIF, source interface identifier, used to get the memory
15 - bit 14: DIF, destination interface identifier, used to get the peripheral
[all …]
|
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
[all …]
|
| H A D | atmel-dma.txt | 1 * Atmel Direct Memory Access Controller (DMA)
4 - compatible: Should be "atmel,<chip>-dma".
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
7 - #dma-cells: Must be <2>, used to represent the number of integer cells in
13 compatible = "atmel,at91sam9g45-dma";
16 #dma-cells = <2>;
19 DMA clients connected to the Atmel DMA controller must use the format
20 described in the dma.txt file, using a three-cell specifier for each channel:
24 1. A phandle pointing to the DMA controller.
[all …]
|
| /openbmc/u-boot/doc/ |
| H A D | README.arm-caches | 1 Disabling I-cache:
2 - Set CONFIG_SYS_ICACHE_OFF
4 Disabling D-cache:
5 - Set CONFIG_SYS_DCACHE_OFF
7 Enabling I-cache:
8 - Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().
10 Enabling D-cache:
11 - Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().
14 - Implement enable_caches() for your platform and enable the I-cache and
15 D-cache from this function. This function is called immediately
[all …]
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | sm501.rst | 15 ----
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
38 the specific set of resources that peripheral requires in order to
41 The centralised memory allocation allows the driver to ensure that the
42 maximum possible resource allocation can be made to the video subsystem
[all …]
|
| /openbmc/qemu/docs/devel/migration/ |
| H A D | qpl-compression.rst | 4 The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
9 and Shared Virtual Memory(``SVM``) technology, they are new features supported
13 For more ``QPL`` introduction, please refer to `QPL Introduction
21 +----------------+ +------------------+
22 | MultiFD Thread | |accel-config tool |
23 +-------+--------+ +--------+---------+
27 +-------+--------+ | Setup IAA
29 +-------+---+----+ |
31 | +-------------+-------+
[all …]
|
| /openbmc/u-boot/drivers/usb/gadget/ |
| H A D | Kconfig | 3 # (a) a peripheral controller, and
6 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
8 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
9 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
10 # - Some systems have both kinds of controllers.
12 # With help from a special transceiver and a "Mini-AB" jack, systems with
13 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
20 host (such as a PC) controlling up to 127 peripheral devices.
21 The USB hardware is asymmetric, which makes it easier to set up:
22 you can't connect a "to-the-host" connector to a peripheral.
[all …]
|
| /openbmc/linux/arch/mips/include/asm/txx9/ |
| H A D | dmac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct txx9dmac_platform_data - Controller configuration parameters
24 * struct txx9dmac_chan_platform_data - Channel configuration parameters
32 * struct txx9dmac_slave - Controller-specific information about a slave
34 * memory-to-peripheral transfers
36 * peripheral-to-memory transfers
37 * @reg_width: peripheral register width
|
| /openbmc/qemu/include/hw/nvram/ |
| H A D | nrf51_nvm.h | 2 * Nordic Semiconductor nRF51 non-volatile memory
4 * It provides an interface to erase regions in flash memory.
8 * + sysbus MMIO regions 0: NVMC peripheral registers
9 * + sysbus MMIO regions 1: FICR peripheral registers
10 * + sysbus MMIO regions 2: UICR peripheral registers
11 * + flash-size property: flash size in bytes.
13 * Accuracy of the peripheral model:
16 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
19 * the COPYING file in the top-level directory.
|
| /openbmc/linux/drivers/gpu/drm/ |
| H A D | drm_mipi_dsi.c | 4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
44 * These functions contain some common logic and helpers to deal with MIPI DSI
60 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
[all …]
|
| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 used to offload memory copies in the network stack and
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
134 has the capability to offload memcpy, xor and pq computation
150 If you have a board based on such a SoC and wish to use DMA for
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
[all …]
|
| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
10 and network peripheral interfaces required for networking & telecommunications.
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
[all …]
|
| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5d2.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D2 SoC
13 * Peripheral identifiers/interrupts.
29 #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
32 #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
45 #define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
46 #define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
47 #define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
19 - Mark Brown <broonie@kernel.org>
[all …]
|
| /openbmc/linux/drivers/firmware/ |
| H A D | qcom_scm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include <linux/reset-controller.h>
22 #include <linux/arm-smccc.h>
38 /* control access to the interconnect path */
82 ret = clk_prepare_enable(__scm->core_clk); in qcom_scm_clk_enable()
86 ret = clk_prepare_enable(__scm->iface_clk); in qcom_scm_clk_enable()
90 ret = clk_prepare_enable(__scm->bus_clk); in qcom_scm_clk_enable()
97 clk_disable_unprepare(__scm->iface_clk); in qcom_scm_clk_enable()
99 clk_disable_unprepare(__scm->core_clk); in qcom_scm_clk_enable()
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/net/can/ |
| H A D | st,stm32-bxcan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
24 Primary mode of the bxCAN peripheral is only relevant if the chip has
27 Not to be used if the peripheral is in single CAN configuration.
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/chrp/ |
| H A D | gg2.h | 2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
11 * This file is subject to the terms and conditions of the GNU General Public
20 * Memory Map (CHRP mode)
23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
|
| /openbmc/linux/Documentation/devicetree/ |
| H A D | overlay-notes.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 This document describes the implementation of the in-kernel
9 companion document to Documentation/devicetree/dynamic-resolution-notes.rst[1]
12 -----------------
14 A Devicetree's overlay purpose is to modify the kernel's live tree, and
23 ---- foo.dts ---------------------------------------------------------------
25 /dts-v1/;
39 ---- foo.dts ---------------------------------------------------------------
44 ---- bar.dts - overlay target location by label ----------------------------
45 /dts-v1/;
[all …]
|
| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2010-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
22 * peripheral clocks, and in most cases there are four options for the clock
29 * clock supplied to the SOC from an external oscillator. The latter is the
30 * memory clock PLL.
40 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
45 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR
16 mode channels of K3 UDMA-P.
19 Block copy channels mainly used for memory to memory transfers, but with
21 directly to memory mapped registers or area.
23 Split channels can be used to service PSI-L based peripherals.
[all …]
|