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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi121 clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
122 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
131 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
152 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
164 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
177 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
187 <&pcc2 IMX7ULP_CLK_LPTPM5>;
[all …]
H A Dimx7ulp-com.dts40 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
H A Dimx7ulp-evk.dts80 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
40 - fsl,imx7ulp-pcc2
92 compatible = "fsl,imx7ulp-pcc2";
H A Dimx7ulp-scg-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dimx-tpm-pwm.yaml53 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
55 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dfsl-imx7ulp-wdt.yaml50 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
51 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
/openbmc/linux/drivers/net/ethernet/i825xx/
H A D82596.c505 volatile unsigned char *pcc2 = (unsigned char *) 0xfff42000; in i596_error() local
507 pcc2[0x28] = 1; in i596_error()
508 pcc2[0x2b] = 0x1d; in i596_error()
626 volatile unsigned char *pcc2 = (unsigned char *) 0xfff42000; in init_i596_mem() local
629 pcc2[0x28] = 1; in init_i596_mem()
630 pcc2[0x2a] = 0x48; in init_i596_mem()
635 pcc2[0x2b] = 0x08; in init_i596_mem()
691 volatile unsigned char *pcc2 = (unsigned char *) 0xfff42000; in init_i596_mem() local
694 pcc2[0x2a] = 0x55; /* Edge sensitive */ in init_i596_mem()
695 pcc2[0x2b] = 0x15; in init_i596_mem()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml202 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dpcc.h12 /* PCC2 */
311 /*PCC2 clocks*/
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml63 <&pcc2 IMX7ULP_CLK_LPTPM5>;
/openbmc/openbmc/poky/meta/recipes-core/ncurses/files/
H A D0001-tic-hang.patch31 - kcbt=\E[Z, use=xterm+pcc2, use=xterm+pcf0,
/openbmc/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h66 /* PCC2 */
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi386 pcc2: pcc2@403F0000 { label
387 compatible = "fsl,imx7ulp-pcc2";
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra114-pinmux.yaml61 pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
H A Dnvidia,tegra30-pinmux.yaml89 pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3,
H A Dnvidia,tegra124-pinmux.yaml66 pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7,
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c149 /* PCC2 */ in imx7ulp_clk_pcc2_init()
181 CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dpinmux.c200 PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dpinmux.c200 PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
/openbmc/u-boot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h306 DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c196 PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-big.dts1163 pcc2 {
1164 nvidia,pins = "pcc2";
H A Dtegra124-nyan-blaze.dts1165 pcc2 {
1166 nvidia,pins = "pcc2";
/openbmc/u-boot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h216 DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),

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