| /openbmc/openpower-occ-control/ |
| H A D | occ_pass_through.hpp | 8 #include <phosphor-logging/log.hpp>
39 /** @brief Ctor to put pass-through d-bus object on the bus
40 * @param[in] path - Path to attach at
46 /** @brief Pass through command to OCC from dbus
47 * @param[in] command - command to pass-through
52 /** @brief Pass through command to OCC from openpower-occ-control
53 * @param[in] command - command to pass-through
60 * @param[in] mode - desired System Power Mode
61 * @param[in] modeData - data associated some Power Modes
68 /** @brief Pass-through occ path on the bus */
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|
| /openbmc/qemu/docs/system/devices/ |
| H A D | usb-u2f.rst | 12 QEMU supports both pass-through of a host U2F key device to a VM,
15 ``u2f-passthru``
16 ----------------
18 The ``u2f-passthru`` device allows you to connect a real hardware
20 are passed through to the physical security key connected to the
23 In addition, the dedicated pass-through allows you to share a single
25 simple host device assignment pass-through.
30 .. parsed-literal::
31 |qemu_system| -usb -device u2f-passthru,hidraw=/dev/hidraw0
33 If you don't specify the device, the ``u2f-passthru`` device will
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|
| H A D | usb.rst | 2 -------------
16 more virtualization-friendly when compared to EHCI and UHCI, thus XHCI
21 |qemu_system| -device qemu-xhci
46 ``-usb`` switch. QEMU will create the UHCI controller as function of
47 the PIIX3 chipset. The USB 1.1 bus will carry the name ``usb-bus.0``.
49 You can use the standard ``-device`` switch to add a EHCI controller to
52 ``-device usb-ehci,id=ehci``. This will give you a USB 2.0 bus named
55 When adding USB devices using the ``-device`` switch you can specify the
58 .. parsed-literal::
60 |qemu_system| -M pc ${otheroptions} \\
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| /openbmc/qemu/docs/devel/ |
| H A D | zoned-storage.rst | 2 zoned-storage
10 https://zonedstorage.io/docs/introduction/zoned-storage
13 -------------------------------------
15 - BLK_Z_HM: The host-managed zoned model only allows sequential writes access
16 to zones. It supports ZBD-specific I/O commands that can be used by a host to
18 - BLK_Z_HA: The host-aware zoned model allows random write operations in
20 - BLK_Z_NONE: The non-zoned model has no zones support. It includes both
21 regular and drive-managed ZBD devices. ZBD-specific I/O commands are not
27 a BlockDriverState graph(for example, raw format on top of file-posix). The
29 the way up to the BlockBackend. If the zoned storage model in file-posix is
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| /openbmc/phosphor-dbus-interfaces/yaml/org/open_power/OCC/ |
| H A D | PassThrough.interface.yaml | 2 Implement to provide pass-through mechanism to the On Chip Controller (OCC).
4 - name: Send
6 Pass through a command to the OCC.
8 - name: command
19 - name: response
29 - name: SetMode
33 - name: mode
37 - name: frequencyPoint
42 - name: status
|
| /openbmc/qemu/hw/vfio/ |
| H A D | pci-quirks.h | 4 * Copyright Red Hat, Inc. 2012-2015
10 * the COPYING file in the top-level directory.
22 * pass reads and writes through to hardware until a value matching the
25 * passing through accesses. This enables devices where PCI config space
27 * provided through vfio.
57 * through a region within a BAR. When enabled, reads and writes are
58 * redirected through to emulated PCI config space. XXX if PCI config space
|
| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/ |
| H A D | api.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
24 #define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
25 #define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
27 #define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
34 #define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
35 #define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
36 #define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
|
| /openbmc/qemu/hw/intc/ |
| H A D | realview_gic.c | 4 * Copyright (c) 2006-2007 CodeSourcery.
15 #include "hw/qdev-properties.h"
21 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in realview_gic_set_irq()
35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
36 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in realview_gic_realize()
39 busdev = SYS_BUS_DEVICE(&s->gic); in realview_gic_realize()
41 /* Pass through outbound IRQ lines from the GIC */ in realview_gic_realize()
44 /* Pass through inbound GPIO lines to the GIC */ in realview_gic_realize()
45 qdev_init_gpio_in(dev, realview_gic_set_irq, numirq - 32); in realview_gic_realize()
47 memory_region_add_subregion(&s->container, 0, in realview_gic_realize()
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|
| H A D | exynos4210_gic.c | 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
29 #include "hw/qdev-properties.h"
51 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); in exynos4210_gic_set_irq()
60 uint32_t n = s->num_cpu; in exynos4210_gic_realize()
63 s->gic = qdev_new("arm_gic"); in exynos4210_gic_realize()
64 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); in exynos4210_gic_realize()
65 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); in exynos4210_gic_realize()
66 gicbusdev = SYS_BUS_DEVICE(s->gic); in exynos4210_gic_realize()
69 /* Pass through outbound IRQ lines from the GIC */ in exynos4210_gic_realize()
72 /* Pass through inbound GPIO lines to the GIC */ in exynos4210_gic_realize()
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| /openbmc/openbmc/meta-ingrasys/meta-zaius/recipes-phosphor/packagegroups/ |
| H A D | packagegroup-obmc-apps.bbappend | 1 # Support OCC pass through and general occ control
3 RDEPENDS:${PN}-inventory:append:zaius = " phosphor-gpio-monitor-presence"
|
| /openbmc/qemu/docs/system/s390x/ |
| H A D | pcidevices.rst | 9 recommended to specify it explicitly so that you can pass s390-specific
12 For example, in order to pass a PCI device ``0000:00:00.0`` through to the
15 qemu-system-s390x ... \
16 -device zpci,uid=1,fid=0,target=hostdev0,id=zpci1 \
17 -device vfio-pci,host=0000:00:00.0,id=hostdev0
32 qemu-system-s390x ... \
33 -device zpci,uid=7,fid=8,target=hostdev0,id=zpci1 \
38 # lspci -v
|
| /openbmc/openbmc-test-automation/lib/ |
| H A D | tally_sheet.py | 15 pass
32 boot_results_fields = collections.OrderedDict([('total', 0), ('pass', 0), ('fail', 0)])
34 boot_results_fields = DotDict([('total', 0), ('pass', 0), ('fail', 0)])
38 boot_test_results.set_sum_fields(['total', 'pass', 'fail'])
40 boot_test_results.set_calc_fields(['total=pass+fail'])
47 boot_test_results.inc_row_field('BMC Power On', 'pass')
48 boot_test_results.inc_row_field('BMC Power Off', 'pass')
57 Boot Type Total Pass Fail
58 ----------------------------------- ----- ---- ----
123 calc_fields A string expression such as 'total=pass+fail'
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| /openbmc/u-boot/arch/mips/include/asm/mach-generic/ |
| H A D | ioremap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * outside the low 32-bit range -- generic pass-through version.
|
| /openbmc/qemu/include/system/ |
| H A D | reset.h | 4 * Copyright (c) 2003-2008 Fabrice Bellard
31 #include "qapi/qapi-events-run-state.h"
41 * they were added, using the three-phase Resettable protocol,
42 * so first all objects go through the enter phase, then all objects
43 * go through the hold phase, and then finally all go through the
68 * @opaque: opaque data to pass to @func
75 * of the 3-phase reset.
91 * @opaque: opaque data to pass to @func
116 * This function performs the low-level work needed to do a complete reset
|
| /openbmc/bmcweb/docs/ |
| H A D | OEM_SCHEMAS.md | 17 Because of that, OEM properties in an open-source project pose many problems
21 possible. Adding machine-specific resources, properties, and types defeats a
22 large amount of reuse, as clients must implement machine-specific APIs, some of
25 and therefore needs to take care when adding new, non-standard APIs, given the
29 quality and testing than their spec-driven alternatives, given the lack of
60 2. Present the new feature and use case to DMTF either through the
62 possible, message the new feature through the normal openbmc communications
75 maintainers, and they will walk you through how to develop the feature under
80 resources, should pass the redfish service validator, should pass the csdl
82 the same level of quality as non-OEM.
|
| H A D | CLIENTS.md | 5 non-exhaustive list of tests and clients that bmcweb is expected to be
8 specification. Entries in the clients category are intended to host user-facing
12 of these tools, the tests pass 100%. There may be cases where we workaround
13 limitations in the testing tools behavior within bmcweb to make the tools pass,
18 Redfish-Service-Validator: A tool to verify through GET requests that bmcweb
20 <https://github.com/DMTF/Redfish-Service-Validator.git>
24 Redfish-Protocol-Validator: A tool to verify the protocol-level interactions
25 with the Redfish wire-protocol, and checks those against the Redfish
26 specification. <https://github.com/DMTF/Redfish-Protocol-Validator>
30 OpenBMC-test-automation: A tool based on robot framework for testing some
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|
| /openbmc/qemu/docs/system/ |
| H A D | device-emulation.rst | 1 .. _device-emulation:
4 ----------------
21 ``--device`` command line option. Running QEMU with the command line
22 options ``--device help`` will list all devices it is aware of. Using
23 the command line ``--device foo,help`` will list the additional
33 machine model you choose (``-M foo``) a number of buses will have been
45 --device foo,bus=pci.0,addr=0,id=foo
46 --device bar,bus=foo.0,addr=1,id=baz
59 devices will be backed by a ``--chardev`` which can redirect the data
61 by ``--blockdev`` which will specify how blocks are handled, for
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| /openbmc/qemu/target/alpha/ |
| H A D | clk_helper.c | 6 * SPDX-License-Identifier: LGPL-2.1-or-later
11 #include "exec/helper-proto.h"
18 * In system mode we have access to a decent high-resolution clock. in helper_load_pcc()
19 * In order to make OS-level time accounting work with the RPCC, in helper_load_pcc()
20 * present it with a well-timed clock fixed at 250MHz. in helper_load_pcc()
22 return (((uint64_t)env->pcc_ofs << 32) in helper_load_pcc()
26 * In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. Just pass through in helper_load_pcc()
|
| /openbmc/u-boot/arch/mips/mach-bmips/include/ |
| H A D | ioremap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * outside the low 32-bit range -- generic pass-through version.
|
| /openbmc/qemu/docs/system/i386/ |
| H A D | hyperv.rst | 1 Hyper-V Enlightenments
6 -----------
11 It may, however, be hard-to-impossible to add support for these interfaces to
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
20 -----
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
23 QEMU, individual enlightenments can be enabled through CPU flags, e.g:
25 .. parsed-literal::
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| /openbmc/u-boot/arch/mips/mach-mscc/include/ |
| H A D | ioremap.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 * outside the low 32-bit range -- generic pass-through version.
|
| /openbmc/openbmc/poky/scripts/lib/devtool/ |
| H A D | utilcmds.py | 1 # Development tool - utility commands plugin
3 # Copyright (C) 2015-2016 Intel Corporation
5 # SPDX-License-Identifier: GPL-2.0-only
25 …logger.warning('-a/--any-recipe option is now always active, and thus the option will be removed i…
43 """Entry point for the devtool 'find-recipe' subcommand"""
50 """Entry point for the devtool 'edit-recipe' subcommand"""
55 """Entry point for the devtool 'configure-help' subcommand"""
88 'bitbake -c configure %s' % args.recipename,
91 pass
107 …configopttext += ''' The ones that are specified through EXTRA_OECONF (which you can change or add…
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| /openbmc/qemu/tests/tcg/multiarch/gdbstub/ |
| H A D | follow-fork-mode-child.py | 1 """Test GDB's follow-fork-mode child.
3 SPDX-License-Identifier: GPL-2.0-or-later
9 """Run through the tests one by one"""
10 gdb.execute("set follow-fork-mode child")
20 pass
28 # Check that the parent single-stepping is turned off.
|
| /openbmc/qemu/docs/ |
| H A D | pci_expander_bridge.txt | 6 PXB is a "light-weight" host bridge in the same PCI domain
12 As opposed to PCI-2-PCI bridge's secondary bus, PXB's bus
15 to recognize the proximity of a pass-through device to
22 [qemu-bin + storage options]
23 -m 2G
24 -object memory-backend-ram,size=1024M,policy=bind,host-nodes=0,id=ram-node0 -numa node,nodeid=0,cpu…
25 -object memory-backend-ram,size=1024M,policy=bind,host-nodes=1,id=ram-node1 -numa node,nodeid=1,cpu…
26 -device pxb,id=bridge1,bus=pci.0,numa_node=1,bus_nr=4 -netdev user,id=nd -device e1000,bus=bridge1,…
27 -device pxb,id=bridge2,bus=pci.0,numa_node=0,bus_nr=8 -device e1000,bus=bridge2,addr=0x3
28 -device pxb,id=bridge3,bus=pci.0,bus_nr=40 -drive if=none,id=drive0,file=[img] -device virtio-blk-p…
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
90 * arch/arm/mach-aspeed/include/mach/regs-scu.h
92 * Copyright (C) 2012-2020 ASPEED Technology Inc.
126 * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
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|