| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | spear600.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
32 vic0: interrupt-controller@f1100000 {
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| H A D | spear320.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear320-pinmux";
21 #gpio-range-cells = <3>;
28 interrupt-parent = <&shirq>;
33 compatible = "st,spear600-fsmc-nand";
34 #address-cells = <1>;
35 #size-cells = <1>;
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| H A D | spear310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
20 compatible = "st,spear310-pinmux";
22 #gpio-range-cells = <3>;
26 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>;
28 #size-cells = <1>;
30 0x40000000 0x0010 /* NAND Base DATA */
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-sni-exiu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Socionext External Interrupt Unit (EXIU)
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
12 #include <linux/interrupt.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 void __iomem *base; member
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
53 * EOI or the interrupt will be jammed on. Of course if a level in exiu_irq_eoi()
54 * triggered interrupt is still asserted then the write will not clear in exiu_irq_eoi()
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| H A D | irq-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
34 * An interrupt must be disabled before configuring it for FIQ generation
80 void __iomem *base; member
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| H A D | irq-al-fic.c | 1 // SPDX-License-Identifier: GPL-2.0
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
37 void __iomem *base; member
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
75 ret = -EINVAL; in al_fic_irq_set_type()
91 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
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| H A D | irq-owl-sirq.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi Owl SoCs SIRQ interrupt controller driver
6 * David Liu <liuwei@actions-semi.com>
14 #include <linux/interrupt.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 /* S900 SIRQ control register offsets, relative to controller base address */
45 /* INTC_EXTCTL reg offsets relative to controller base address */
51 void __iomem *base; member
98 val = readl_relaxed(data->base + data->params->reg_offset[index]); in owl_sirq_read_extctl()
99 if (data->params->reg_shared) in owl_sirq_read_extctl()
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| H A D | irq-renesas-rza1.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/interrupt.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #define ICR0 0 /* Interrupt Control Register 0 */
27 #define ICR0_NMIF BIT(1) /* NMI Interrupt Request */
29 #define ICR1 2 /* Interrupt Control Register 1 */
38 #define IRQRR 4 /* IRQ Interrupt Request Register */
43 void __iomem *base; member
51 return data->domain->host_data; in irq_data_to_priv()
60 tmp = readw_relaxed(priv->base + IRQRR); in rza1_irqc_eoi()
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| H A D | irq-brcmstb-l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
5 * Copyright (C) 2014-2024 Broadcom
18 #include <linux/interrupt.h>
34 /* Register offsets in the L2 latched interrupt controller */
44 /* Register offsets in the L2 level interrupt controller */
48 .cpu_clear = -1, /* Register not present */
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
69 * register and pending interrupt is acknowledged by setting a bit.
81 u32 mask = d->mask; in brcmstb_l2_mask_and_ack()
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| H A D | irq-ti-sci-inta.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments' K3 Interrupt Aggregator irqchip driver
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/interrupt.h>
24 #include <asm-generic/msi.h>
44 * struct ti_sci_inta_event_desc - Description of an event coming to
45 * Interrupt Aggregator. This serves
49 * @hwirq: Hwirq of the incoming interrupt
59 * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
60 * of Interrupt Aggregator.
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| H A D | irq-bcm7120-l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7120 style Level 2 interrupt controller driver
19 #include <linux/interrupt.h>
28 /* Register offset in the L2 interrupt controller */
58 struct bcm7120_l2_intc_data *b = data->b; in bcm7120_l2_intc_irq_handle()
64 for (idx = 0; idx < b->n_words; idx++) { in bcm7120_l2_intc_irq_handle()
65 int base = idx * IRQS_PER_WORD; in bcm7120_l2_intc_irq_handle() local
67 irq_get_domain_generic_chip(b->domain, base); in bcm7120_l2_intc_irq_handle()
72 pending = irq_reg_readl(gc, b->stat_offset[idx]) & in bcm7120_l2_intc_irq_handle()
73 gc->mask_cache & in bcm7120_l2_intc_irq_handle()
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| H A D | irq-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver code for Tegra's Legacy Interrupt Controller
7 * Heavily based on the original arch/arm/mach-tegra/irq.c code:
24 #include <dt-bindings/interrupt-controller/arm-gic.h>
62 { .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
63 { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
64 { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
69 void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; member
84 void __iomem *base = (void __iomem __force *)d->chip_data; in tegra_ictlr_write_mask() local
87 mask = BIT(d->hwirq % 32); in tegra_ictlr_write_mask()
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| H A D | irq-ti-sci-intr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments' K3 Interrupt Router irqchip driver
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
22 * Interrupt Router IRQ domain.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
62 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_irq_domain_translate()
64 if (fwspec->param_count != 1) in ti_sci_intr_irq_domain_translate()
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| /openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | marvell.txt | 2 ---------------------------------------
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
36 - interrupts : Interrupt from the switch
37 - interrupt-controller : Indicates the switch is itself an interrupt
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| /openbmc/u-boot/doc/device-tree-bindings/gpu/ |
| H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | loongson,pch-pic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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| H A D | loongson,pch-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
32 loongson,msi-num-vecs:
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| H A D | fsl,ls-scfg-msi.txt | 5 - compatible: should be "fsl,<soc-name>-msi" to identify
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
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| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
21 #include <linux/interrupt.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
116 * @base: virtual memory area
120 * @parent_rate: I2C clock parent rate in MHz
126 void __iomem *base; member
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| /openbmc/linux/drivers/watchdog/ |
| H A D | starfive-wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
25 * [0]: Write 1 to clear interrupt
36 * [1]: interrupt enable && watchdog enable
56 #define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
88 unsigned int int_clr; /* Watchdog Interrupt Clear Register */
90 unsigned int int_status; /* Watchdog Interrupt Status Register */
95 bool intclr_check; /* whether need to check it before clearing interrupt */
103 void __iomem *base; member
150 ret = clk_prepare_enable(wdt->apb_clk); in starfive_wdt_enable_clock()
152 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n"); in starfive_wdt_enable_clock()
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| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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| /openbmc/linux/include/linux/gpio/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/pinctrl/pinconf-generic.h>
46 * struct gpio_irq_chip - GPIO interrupt controller
59 * Interrupt translation domain; responsible for mapping between GPIO
76 * If non-NULL, will be set as the parent of this GPIO interrupt
77 * controller's IRQ domain to establish a hierarchical interrupt
79 * interrupt support.
86 * This callback translates a child hardware IRQ offset to a parent
87 * hardware IRQ offset on a hierarchical interrupt chip. The child
88 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
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| /openbmc/linux/drivers/staging/vme_user/ |
| H A D | vme_tsi148.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
80 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
84 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
102 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
122 bridge = tsi148_bridge->driver_priv; in tsi148_MB_irqhandler()
126 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
127 dev_err(tsi148_bridge->parent, "VME Mailbox %d received: 0x%x\n", in tsi148_MB_irqhandler()
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