| /openbmc/linux/drivers/usb/phy/ |
| H A D | phy-gpio-vbus-usb.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
20 #include <linux/usb/otg.h>
24 * A simple GPIO VBUS sensing driver for B peripheral only devices
26 * a regulator to limit the current drawn from VBUS.
39 int vbus; member
45 * This driver relies on "both edges" triggering. VBUS has 100 msec to
60 struct regulator *vbus_draw = gpio_vbus->vbus_draw; in set_vbus_draw()
67 enabled = gpio_vbus->vbus_draw_enabled; in set_vbus_draw()
74 gpio_vbus->vbus_draw_enabled = 1; in set_vbus_draw()
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| H A D | phy-generic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * NOP USB transceiver for all USB transceiver which are either built-in
16 #include <linux/dma-mapping.h>
18 #include <linux/usb/otg.h>
27 #include "phy-generic.h"
48 struct usb_phy_generic *nop = dev_get_drvdata(x->dev); in nop_set_suspend()
50 if (!IS_ERR(nop->clk)) { in nop_set_suspend()
52 clk_disable_unprepare(nop->clk); in nop_set_suspend()
54 clk_prepare_enable(nop->clk); in nop_set_suspend()
62 if (!nop->gpiod_reset) in nop_reset()
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| H A D | phy-mv-usb.c | 1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/usb/otg.h>
26 #include "phy-mv-usb.h"
28 #define DRIVER_DESC "Marvell USB OTG transceiver driver"
33 static const char driver_name[] = "mv-otg";
52 static int mv_otg_set_vbus(struct usb_otg *otg, bool on) in mv_otg_set_vbus() argument
54 struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy); in mv_otg_set_vbus()
55 if (mvotg->pdata->set_vbus == NULL) in mv_otg_set_vbus()
56 return -ENODEV; in mv_otg_set_vbus()
58 return mvotg->pdata->set_vbus(on); in mv_otg_set_vbus()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
19 Enable this to support the USB OTG transceiver in AB8500 chip.
24 tristate "Freescale USB OTG Transceiver Driver"
29 Enable this to support Freescale USB OTG transceiver.
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
68 Enable this to support the USB OTG transceiver on TWL6030
69 family chips. This TWL6030 transceiver has the VBUS and ID GND
70 and OTG SRP events capabilities. For all other transceiver functionality
73 The definition of internal PHY APIs are in the mach-omap2 layer.
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| /openbmc/linux/drivers/phy/motorola/ |
| H A D | phy-cpcap-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * board-mapphone-usb.c and cpcap-usb-det.c:
8 * Copyright (C) 2007 - 2011 Motorola, Inc.
26 #include <linux/mfd/motorola-cpcap.h>
124 struct iio_channel *vbus; member
136 error = iio_read_channel_processed(ddata->vbus, &value); in cpcap_usb_vbus_valid()
140 dev_err(ddata->dev, "error reading VBUS: %i\n", error); in cpcap_usb_vbus_valid()
145 static int cpcap_usb_phy_set_host(struct usb_otg *otg, struct usb_bus *host) in cpcap_usb_phy_set_host() argument
147 otg->host = host; in cpcap_usb_phy_set_host()
149 otg->state = OTG_STATE_UNDEFINED; in cpcap_usb_phy_set_host()
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| /openbmc/linux/drivers/usb/chipidea/ |
| H A D | otg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * otg.c - ChipIdea USB IP core OTG driver
11 * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
15 #include <linux/usb/otg.h>
21 #include "otg.h"
25 * hw_read_otgsc - returns otgsc register bits value.
35 * If using extcon framework for VBUS and/or ID signal in hw_read_otgsc()
38 cable = &ci->platdata->vbus_extcon; in hw_read_otgsc()
39 if (!IS_ERR(cable->edev) || ci->role_switch) { in hw_read_otgsc()
40 if (cable->changed) in hw_read_otgsc()
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| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | mt6360_charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gene Chen <gene_chen@richtek.com>
14 Provides Battery Charger, Boost for OTG devices and BC1.2 detection.
18 const: mediatek,mt6360-chg
20 richtek,vinovp-microvolt:
25 usb-otg-vbus-regulator:
27 description: OTG boost regulator.
32 - compatible
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| H A D | richtek,rt9467.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
11 - ChiaEn Wu <chiaen_wu@richtek.com>
14 RT9467 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
16 MOSFETs, input current sensing and regulation, high-accuracy voltage
20 The RT9467 also features USB On-The-Go (OTG) support. It also integrates
21 D+/D- pin for USB host/charging port detection.
24 https://www.richtek.com/assets/product_file/RT9467/DS9467-01.pdf
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | allwinner,suniv-f1c100s-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,suniv-f1c100s-usb-phy
24 reg-names:
29 description: USB OTG PHY bus clock
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| H A D | allwinner,sun8i-v3s-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-v3s-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
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| H A D | allwinner,sun5i-a13-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun5i-a13-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
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| H A D | allwinner,sun8i-a23-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a23-usb-phy
20 - allwinner,sun8i-a33-usb-phy
24 - description: PHY Control registers
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| H A D | allwinner,sun50i-a64-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
24 - description: PHY Control registers
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| H A D | allwinner,sun50i-h6-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun50i-h6-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
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| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | allwinner,sun6i-a31-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun6i-a31-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
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| H A D | allwinner,sun8i-r40-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-r40-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
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| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| H A D | allwinner,sun8i-a83t-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
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| H A D | allwinner,sun4i-a10-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
24 - description: PHY Control registers
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| /openbmc/linux/include/linux/platform_data/ |
| H A D | mv_usb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 struct mv_usb_addon_irq *id; /* Only valid for OTG. ID pin change*/
26 struct mv_usb_addon_irq *vbus; /* valid for OTG/UDC. VBUS change*/ member
28 /* only valid for HCD. OTG or Host only*/
31 /* This flag is used for that needs id pin checked by otg */
38 int (*set_vbus)(unsigned int vbus);
|
| /openbmc/linux/drivers/usb/musb/ |
| H A D | da8xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
5 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2005-2006 by Texas Instruments
23 #include <linux/dma-mapping.h>
32 /* USB 2.0 OTG module registers */
46 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
76 * - not read/write INTRUSB/INTRUSBE (except during
78 * - use INTSET/INTCLR instead.
82 * da8xx_musb_enable - enable interrupts
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| H A D | tusb6010.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TUSB6010 USB 2.0 OTG Dual Role controller
9 * - Driver assumes that interface to external host (main CPU) is
27 #include <linux/dma-mapping.h>
51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
71 rev = musb->tusb_revision; in tusb_print_revision()
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
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| /openbmc/linux/include/linux/usb/ |
| H A D | otg-fsm.h | 1 // SPDX-License-Identifier: GPL-2.0+
16 #define OTG_STS_SELECTOR 0xF000 /* OTG status selector, according to
17 * OTG and EH 2.0 Chapter 6.2.3
18 * Table:6-4
22 * OTG and EH 2.0 Charpter 6.2.3
23 * Table:6-5
29 /* Standard OTG timers */
49 * struct otg_fsm - OTG state machine according to the OTG spec
51 * OTG hardware Inputs
54 * @id: TRUE for B-device, FALSE for A-device.
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | dwc2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
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