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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
26 4: I2C port 1
27 5: I2C port 3
28 6: I2C port 2
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-class-udc6 Indicates if an OTG A-Host supports HNP at an alternate port.
14 Indicates if an OTG A-Host supports HNP at this port.
22 Indicates if an OTG A-Host enabled HNP support.
30 Indicates the current negotiated speed at this port.
38 Indicates that this port is the default Host on an OTG session
47 Indicates that this port support OTG.
55 Indicates the maximum USB speed supported by this port.
81 states are: 'not-attached', 'attached', 'powered',
/openbmc/u-boot/drivers/usb/host/
H A Dehci-faraday.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
23 struct fotg210_regs otg; member
28 return !readl(&regs->usb.easstr); in ehci_is_fotg2xx()
41 ret = (void __iomem *)((ulong)ctrl->hcor - 0x10); in faraday_ehci_get_port_speed()
43 spd = OTGCSR_SPD(readl(&regs->otg.otgcsr)); in faraday_ehci_get_port_speed()
45 spd = BMCSR_SPD(readl(&regs->usb.bmcsr)); in faraday_ehci_get_port_speed()
58 printf("ehci-faraday: invalid device speed\n"); in faraday_ehci_get_port_speed()
65 uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) in faraday_ehci_get_portsc_register() argument
68 if (port) { in faraday_ehci_get_portsc_register()
[all …]
H A Dehci-mx6.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <usb/ehci-ci.h>
14 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sys_proto.h>
19 #include <asm/mach-types.h>
58 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
59 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
60 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
94 chrg_detect = &anatop->usb1_chrg_detect; in usb_power_config()
[all …]
H A Dehci-mx5.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <usb/ehci-ci.h>
13 #include <asm/arch/imx-regs.h>
34 /* OTG wakeup intr enable */
36 /* OTG power mask */
38 /* OTG power pin polarity */
50 /* OTG Polarity of Overcurrent */
52 /* OTG Disable Overcurrent Event */
58 /* OTG Power Pin Polarity */
79 int mxc_set_usbcontrol(int port, unsigned int flags) in mxc_set_usbcontrol() argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
[all …]
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
23 connected to the Glue to serve as OTG ID change detection.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
[all …]
H A Dfsl-usb.txt9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
13 also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
14 - phy_type : For multi port host USB controllers, should be one of
17 - reg : Offset and length of the register set for the device
18 - port0 : boolean; if defined, indicates port0 is connected for
19 fsl-usb2-mph compatible controllers. Either this property or
20 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
22 - port1 : boolean; if defined, indicates port1 is connected for
[all …]
/openbmc/linux/drivers/extcon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 host USB ports. Many of 30-pin connectors including PDMI are
25 tristate "X-Power AXP288 EXTCON support"
30 and USB MUX switching by X-Power AXP288 PMIC.
40 port accessory detector and switch. The FSA9480 is fully controlled using
42 and UART data to use a common connector port.
55 Say Y here to enable extcon support for USB OTG ports controlled by
85 Maxim MAX14577/77836. The MAX14577/77836 MUIC is a USB port accessory
89 tristate "Maxim MAX3355 USB OTG EXTCON Support"
92 If you say yes here you get support for the USB OTG role detection by
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "pxa-regs.h"
12 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
13 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
14 Protocol Port Support */
15 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
17 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
19 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
44 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
45 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
[all …]
/openbmc/linux/Documentation/driver-api/usb/
H A Dgadget.rst11 This document presents a Linux-USB "Gadget" kernel mode API, for use
17 - Supports USB 2.0, for high speed devices which can stream data at
20 - Handles devices with dozens of endpoints just as well as ones with
21 just two fixed-function ones. Gadget drivers can be written so
22 they're easy to port to new hardware.
24 - Flexible enough to expose more complex USB device capabilities such
28 - USB "On-The-Go" (OTG) support, in conjunction with updates to the
29 Linux-USB host side.
31 - Sharing data structures and API models with the Linux-USB host side
32 API. This helps the OTG support, and looks forward to more-symmetric
[all …]
/openbmc/linux/Documentation/firmware-guide/acpi/
H A Dextcon-intel-int3496.rst6 devices with an acpi-id of INT3496, such as found for example on
9 This ACPI device describes how the OS can read the id-pin of the devices'
10 USB-otg port, as well as how it optionally can enable Vbus output on the
11 otg port and how it can optionally control the muxing of the data pins
18 Index 0 The input gpio for the id-pin, this is always present and valid
19 Index 1 The output gpio for enabling Vbus output from the device to the otg
20 port, write 1 to enable the Vbus output (this gpio descriptor may
/openbmc/linux/drivers/usb/musb/
H A Dmusb_virthub.c1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver virtual root hub support
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
29 spin_lock_irqsave(&musb->lock, flags); in musb_host_finish_resume()
31 power = musb_readb(musb->mregs, MUSB_POWER); in musb_host_finish_resume()
33 musb_dbg(musb, "root port resume stopped, power %02x", power); in musb_host_finish_resume()
34 musb_writeb(musb->mregs, MUSB_POWER, power); in musb_host_finish_resume()
41 musb->is_active = 1; in musb_host_finish_resume()
42 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND | MUSB_PORT_STAT_RESUME); in musb_host_finish_resume()
[all …]
/openbmc/u-boot/drivers/usb/phy/
H A Drockchip_usb2_phy.c1 // SPDX-License-Identifier: GPL-2.0+
25 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
26 * @port_reset: usb otg per-port reset register
27 * @soft_con: software control usb otg register
48 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
57 tmp = en ? reg->enable : reg->disable; in property_enable()
58 mask = GENMASK(reg->bitend, reg->bitstart); in property_enable()
59 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in property_enable()
61 writel(val, pdata->regs_phy + reg->offset); in property_enable()
67 struct dwc2_plat_otg_data *pdata = dev->pdata; in otg_phy_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dphy-stm32-usbphyc.txt3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
16 |_ UTMI switch_______| OTG controller
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
[all …]
/openbmc/linux/Documentation/usb/
H A Dchipidea.rst5 1. How to test OTG FSM(HNP and SRP)
6 -----------------------------------
8 To show how to demo OTG HNP and SRP functions via sys input files
11 1.1 How to enable OTG FSM
12 -------------------------
18 variables for otg fsm, mount debugfs, there are 2 files
19 which can show otg fsm variables and some controller registers value::
21 cat /sys/kernel/debug/ci_hdrc.0/otg
29 otg-rev = <0x0200>;
30 adp-disable;
[all …]
/openbmc/linux/drivers/usb/phy/
H A Dphy-fsl-usb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 #include <linux/usb/otg-fsm.h>
5 #include <linux/usb/otg.h>
30 /* bit 9-8 are async schedule park mode count */
37 /* bit 23-16 are interrupt threshold control */
77 /* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
99 /* bit 11-10 are line status */
106 /* bit 15-14 are port indicator control */
113 /* bit 19-16 are port test control */
122 /* bit 27-26 are port speed */
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dulcb-kf.dtsi1 // SPDX-License-Identifier: GPL-2.0
18 #clock-cells = <0>;
19 compatible = "gpio-mux-clock";
21 select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>;
24 hdmi1-out {
25 compatible = "hdmi-connector";
28 port {
30 remote-endpoint = <&adv7513_out>;
35 accel_3v3: regulator-acc-3v3 {
36 compatible = "regulator-fixed";
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dusb-omap1.h15 * - "A" connector (rectagular)
17 * - "B" connector (squarish) or "Mini-B"
19 * - "Mini-AB" connector (very similar to Mini-B)
20 * ... for OTG use as device OR host, initialize "otg"
24 u8 otg; /* port number, 1-based: usb1 == 2 */ member
26 const char *extcon; /* extcon device for OTG */
30 /* implicitly true if otg: host supports remote wakeup? */
35 * 2 == usb0-only, using internal transceiver

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