| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | xlnx,xps-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
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| H A D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
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| H A D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
16 independently for each timer.
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
27 - arm,sp804
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| H A D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
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| H A D | nvidia,tegra186-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 timer
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
14 counter. Each NV timer selects its timing reference signal from the 1 MHz
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
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| /openbmc/qemu/include/hw/ |
| H A D | ptimer.h | 2 * General purpose implementation of a simple periodic countdown timer.
11 #include "qemu/timer.h"
14 * The ptimer API implements a simple periodic countdown timer.
15 * The countdown timer has a value (which can be read and written via
21 * and keep counting down, or to stop (as a one-shot timer).
23 * A transaction-based API is used for modifying ptimer state: all calls
27 * of the timer after all the changes in the transaction, and call the
29 * list of state-modifying functions and detailed semantics of the callback.)
33 * to stderr when the guest attempts to enable the timer.
40 * timer behaviour. For a new device using ptimers, you should not
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| /openbmc/linux/Documentation/virt/kvm/x86/ |
| H A D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
20 One of the most complicated parts of the X86 platform, and specifically,
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
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| /openbmc/qemu/include/qemu/ |
| H A D | timer.h | 6 #include "qemu/host-utils.h"
23 * The real time clock should be used only for stuff which does not
29 * The virtual clock only runs during the emulation. It stops
56 * QEMU Timer attributes:
58 * An individual timer may be given one or multiple attributes when initialized.
59 * Each attribute corresponds to one bit. Attributes modify the processing
68 * used for the subsystems that operate outside the guest core. Applicable only
139 * Determines whether a clock's default timer list
143 * the timer list. The return value may be outdated by the time it is acted
146 * Returns: true if the clock's default timer list
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| /openbmc/linux/Documentation/devicetree/bindings/soc/microchip/ |
| H A D | atmel,at91rm9200-tcb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
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| /openbmc/linux/arch/parisc/kernel/ |
| H A D | time.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * 1994-07-02 Alan Modra
11 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
45 static unsigned long clocktick __ro_after_init; /* timer cycles per tick */
48 * We keep time on PA-RISC Linux by using the Interval Timer which is
49 * a pair of registers; one is read-only and one is write-only; both
50 * accessed through CR16. The read-only register is 32 or 64 bits wide,
51 * and increments by 1 every CPU clock tick. The architecture only
53 * rate of 1. The write-only register is 32-bits wide. When the lowest
54 * 32 bits of the read-only register compare equal to the write-only
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| /openbmc/linux/arch/arm/mach-at91/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
34 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
45 Select this if you are using one of Microchip's SAMA5D3 family SoC.
59 Select this if you are using one of Microchip's SAMA5D4 family SoC.
70 Select this if you are using one of Microchip's SAMA7G5 family SoC.
110 Select this if you are using one of those Microchip SoC:
147 bool "Periodic Interval Timer (PIT) support"
153 Timer. It has a relatively low resolution and the TC Block clocksource
157 bool "Timer Counter Blocks (TCB) support"
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| /openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | marvell,cn10624-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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| /openbmc/qemu/hw/watchdog/ |
| H A D | wdt_ib700.c | 24 #include "qemu/timer.h"
47 QEMUTimer *timer; member
52 /* This is the timer. We use a global here because the watchdog
53 * code ensures there is only one watchdog (it is located at a fixed,
54 * unchangeable IO port, so there could only ever be one anyway).
57 /* A write to this register enables the timer. */
70 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); in ib700_write_enable_reg()
73 /* A write (of any value) to this register disables the timer. */
80 timer_del(s->timer); in ib700_write_disable_reg()
91 timer_del(s->timer); in ib700_timer_expired()
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| /openbmc/u-boot/lib/efi_selftest/ |
| H A D | efi_selftest_watchdog.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * The 'watchdog timer' unit test checks that the watchdog timer
9 * a timer reset.
11 * The 'watchdog reboot' unit test checks that the watchdog timer
12 * actually reboots the system after a timeout. The test is only
52 /* Reset watchdog timer to one second */ in notify()
53 ret = boottime->set_watchdog_timer(1, 0, 0, NULL); in notify()
55 notify_context->status = ret; in notify()
57 notify_context->timer_ticks++; in notify()
63 * Create two timer events.
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| /openbmc/linux/include/soc/at91/ |
| H A D | atmel_tcb.h | 2 * Timer/Counter Unit (TC) registers.
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
38 * @counter_width: size in bits of a timer counter register
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
40 * @has_qdec: boolean indicating if a timer counter has a quadrature
50 * struct atmel_tc - information about a Timer/Counter Block
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| /openbmc/linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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| /openbmc/linux/Documentation/admin-guide/pm/ |
| H A D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
38 entity which appears to be fetching instructions that belong to one sequence
42 First, if the whole processor can only follow one sequence of instructions (one
46 Second, if the processor is multi-core, each core in it is able to follow at
47 least one program at a time. The cores need not be entirely independent of each
49 work physically in parallel with each other, so if each of them executes only
50 one program, those programs run mostly independently of each other at the same
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | mac_via.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
59 * state-control line SEL" on all but IIfx
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
117 * correspond to a VIA work-alike named 'EVR'. */
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-cs5535.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #define DRV_NAME "cs5535-clockevt"
26 * We are using the 32.768kHz input clock - it's the only one that has the
53 * as clock event sources - not as good as a HPET or APIC, but certainly
55 * a simplified one designed specifically to act as a clock event source.
59 static void disable_timer(struct cs5535_mfgpt_timer *timer) in disable_timer() argument
62 cs5535_mfgpt_write(timer, MFGPT_REG_SETUP, in disable_timer()
67 static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta) in start_timer() argument
69 cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta); in start_timer()
70 cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); in start_timer()
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| /openbmc/linux/drivers/char/ipmi/ |
| H A D | ipmi_watchdog.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * A watchdog timer based upon the IPMI interface.
43 * This is ugly, but I've determined that x86 is the only architecture
57 * The IPMI command/response information for the watchdog timer.
98 * pre-timeout in seconds.
109 * Setting/getting the watchdog timer value. This is for bytes 5 and
135 /* The pre-timeout is disabled by default. */
160 static int ifnum_to_use = -1;
184 return -EINVAL; in set_param_timeout()
187 return -EINVAL; in set_param_timeout()
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| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_event_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 * This file contains CSS-API events functionality
64 /** Timer event for measuring the SP side latencies. It contains the
65 32-bit timer value from the SP */
110 The exposure ID is unique only within a logical stream and it is
111 only generated on systems that have an input system (such as 2400
118 Exposure IDs start at IA_CSS_MIN_EXPOSURE_ID, increment by one
128 /** Firmware warning code, only for WARNING events. */
130 /** Firmware module id, only for ASSERT events, should be logged by driver. */
132 /** Firmware line number, only for ASSERT events, should be logged by driver. */
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| /openbmc/u-boot/arch/arm/include/asm/arch-aspeed/ |
| H A D | timer.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 /* Each timer has 4 control bits in ctrl1 register.
10 * such that timer X uses bits (4 * X - 4):(4 * X - 1)
11 * If the timer does not support PWM, bit 4 is reserved.
19 #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
27 * separate devices. Since only one timer is needed at the moment, making
28 * it this just one device.
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| /openbmc/linux/drivers/watchdog/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 bool "Watchdog Timer Support"
10 If you say Y here (and to one of the following options) and create a
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
34 tristate "WatchDog Timer Driver Core"
36 Say Y here if you want to use the new watchdog timer driver core.
37 This driver provides a framework for all watchdog timer drivers
45 to stop the timer if the process managing it closes the file
51 bool "Update boot-enabled watchdog until userspace takes over"
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| /openbmc/linux/kernel/time/ |
| H A D | tick-sched.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 * struct tick_sched - sched tick emulation and no idle tick control/stats
30 * @do_timer_last: CPU was the last one doing do_timer before going idle
31 * @got_idle_tick: Tick timer function has run with @inidle set
37 * timer is modified for nohz sleeps. This is necessary
38 * to resume the tick timer operation in the timeline
44 * @nohz_mode: Mode - one state of tick_nohz_mode
47 * @timer_expires: Anticipated timer expiration time (in case sched tick is stopped)
48 * @next_timer: Expiry time of next expiring timer for debugging purpose only
49 * @idle_expires: Next tick in idle, for debugging purpose only
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| /openbmc/qemu/include/hw/timer/ |
| H A D | cmsdk-apb-dualtimer.h | 2 * ARM CMSDK APB dual-timer emulation
13 * This is a model of the "APB dual-input timer" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
21 * + sysbus IRQ 0: combined timer interrupt TIMINTC
22 * + sysbus IRO 1: timer block 1 interrupt TIMINT1
23 * + sysbus IRQ 2: timer block 2 interrupt TIMINT2
34 #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
38 /* One of the two identical timer modules in the dual-timer module */
41 struct ptimer_state *timer; member
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