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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
[all …]
/openbmc/linux/drivers/tty/
H A Dn_gsm.c1 // SPDX-License-Identifier: GPL-2.0
9 * tty -> DLCI fifo -> scheduler -> GSM MUX data queue ---o-> ldisc
10 * control message -> GSM MUX control queue --´
13 * ldisc -> gsm_queue() -o--> tty
14 * `-> gsm_control_response()
24 * Review the locking/move to refcounts more (mux now moved to an
29 * Do we need a 'which mux are you' ioctl to correlate mux and tty sets
95 * Semi-arbitrary buffer size limits. 0710 is normally run with 32-64 byte
101 /* SOF, ADDR, CTRL, LEN1, LEN2, ..., FCS, EOF */
106 * struct gsm_mux_net - network interface
[all …]
/openbmc/linux/include/net/caif/
H A Dcaif_layer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson AB 2010
10 #include <linux/list.h>
21 * caif_assert() - Assert function for CAIF.
36 * enum caif_ctrlcmd - CAIF Stack Control Signaling sent in layer.ctrlcmd().
50 * @CAIF_CTRLCMD_DEINIT_RSP: Called when de-initialization is
79 * enum caif_modemcmd - Modem Control Signaling, sent from CAIF Client
104 * enum caif_direction - CAIF Packet Direction.
115 * struct cflayer - CAIF Stack layer.
119 * @node: List node used when layer participate in a list.
[all …]
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
8 /* At the begin of the runtime phase the IP MUX channel shall created. */
13 channel_id = ipc_imem_channel_alloc(ipc_mux->imem, ipc_mux->instance_id, in ipc_mux_channel_create()
17 dev_err(ipc_mux->dev, in ipc_mux_channel_create()
18 "allocation of the MUX channel id failed"); in ipc_mux_channel_create()
19 ipc_mux->state = MUX_S_ERROR; in ipc_mux_channel_create()
20 ipc_mux->event = MUX_E_NOT_APPLICABLE; in ipc_mux_channel_create()
24 /* Establish the MUX channel in blocking mode. */ in ipc_mux_channel_create()
25 ipc_mux->channel = ipc_imem_channel_open(ipc_mux->imem, channel_id, in ipc_mux_channel_create()
[all …]
H A Diosm_ipc_mux_codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
12 /* Test the link power state and send a MUX command in blocking mode. */
16 struct iosm_mux *ipc_mux = ipc_imem->mux; in ipc_mux_tq_cmd_send()
19 skb_queue_tail(&ipc_mux->channel->ul_list, acb->skb); in ipc_mux_tq_cmd_send()
20 ipc_imem_ul_send(ipc_mux->imem); in ipc_mux_tq_cmd_send()
27 struct completion *completion = &ipc_mux->channel->ul_sem; in ipc_mux_acb_send()
28 int ret = ipc_task_queue_send_task(ipc_mux->imem, ipc_mux_tq_cmd_send, in ipc_mux_acb_send()
29 0, &ipc_mux->acb, in ipc_mux_acb_send()
30 sizeof(ipc_mux->acb), false); in ipc_mux_acb_send()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
[all …]
/openbmc/linux/net/caif/
H A Dcfmuxl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2010
44 static void cfmuxl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
54 this->layer.receive = cfmuxl_receive; in cfmuxl_create()
55 this->layer.transmit = cfmuxl_transmit; in cfmuxl_create()
56 this->layer.ctrlcmd = cfmuxl_ctrlcmd; in cfmuxl_create()
57 INIT_LIST_HEAD(&this->srvl_list); in cfmuxl_create()
58 INIT_LIST_HEAD(&this->frml_list); in cfmuxl_create()
59 spin_lock_init(&this->transmit_lock); in cfmuxl_create()
60 spin_lock_init(&this->receive_lock); in cfmuxl_create()
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
65 * @subname: (optional) additional ctrl setting name, e.g. rts, cts
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
95 * struct mvebu_mpp_mode - link ctrl and settings
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pctl_res_idx: index of base address for pin-bank registers.
[all …]
H A Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
31 #include "pinctrl-samsung.h"
36 /* list of all possible config options supported */
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
[all …]
/openbmc/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/openbmc/qemu/chardev/
H A Dchar.c4 * Copyright (c) 2003-2008 Fabrice Bellard
28 #include "monitor/qmp-helpers.h"
29 #include "qemu/config-file.h"
30 #include "qemu/error-report.h"
31 #include "qemu/qemu-print.h"
34 #include "qapi/qapi-commands-char.h"
44 #include "chardev-internal.h"
56 CharBackend *be = s->be; in chr_be_event()
58 if (!be || !be->chr_event) { in chr_be_event()
62 be->chr_event(be->opaque, event); in chr_be_event()
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dpcl818.c1 // SPDX-License-Identifier: GPL-2.0
6 * Description: Advantech PCL-818 cards, PCL-718
8 * Devices: [Advantech] PCL-818L (pcl818l), PCL-818H (pcl818h),
9 * PCL-818HD (pcl818hd), PCL-818HG (pcl818hg), PCL-818 (pcl818),
10 * PCL-718 (pcl718)
14 * Differences are only at maximal sample speed, range list and FIFO
18 * PCL-818HD and PCL-818HG support 1kword FIFO. Driver support this FIFO
37 * Options for PCL-818L:
38 * [0] - IO Base
39 * [1] - IRQ (0=disable, 2, 3, 4, 5, 6, 7)
[all …]
H A Dpcl816.c1 // SPDX-License-Identifier: GPL-2.0
4 * Comedi driver for Advantech PCL-816 cards
12 * Description: Advantech PCL-816 cards, PCL-814
13 * Devices: [Advantech] PCL-816 (pcl816), PCL-814B (pcl814b)
16 * Updated: Tue, 2 Apr 2002 23:15:21 -0800
26 * [0] - IO Base
27 * [1] - IRQ (0=disable, 2, 3, 4, 5, 6, 7)
28 * [2] - DMA (0=disable, 1, 3)
29 * [3] - 0, 10=10MHz clock for 8254
114 struct pcl816_private *devpriv = dev->private; in pcl816_ai_setup_dma()
[all …]
H A Dcb_pcidas.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2001-2003 Ivan Martinez <imr@oersted.dtu.dk>
10 * COMEDI - Linux Control and Measurement Device Interface
11 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
16 * Description: MeasurementComputing PCI-DAS series
18 * Devices: [Measurement Computing] PCI-DAS1602/16 (cb_pcidas),
19 * PCI-DAS1602/16jr, PCI-DAS1602/12, PCI-DAS1200, PCI-DAS1200jr,
20 * PCI-DAS1000, PCI-DAS1001, PCI_DAS1002
23 * Updated: 2003-3-11
36 * (i.e. 4-5-6-7, 2-3-4,...), and must all have the same
[all …]
H A Dpcl812.c1 // SPDX-License-Identifier: GPL-2.0
8 * card: PCL-812, PCL-812PG, PCL-813, PCL-813B
11 * card: ACL-8112DG, ACL-8112HG, ACL-8112PG, ACL-8113, ACL-8216
14 * card: ISO-813, A-821PGH, A-821PGL, A-821PGL-NDA, A-822PGH, A-822PGL,
15 * driver: iso813, a821pgh, a-821pgl, a-821pglnda, a822pgh, a822pgl,
16 * card: A-823PGH, A-823PGL, A-826PG
22 * Description: Advantech PCL-812/PG, PCL-813/B,
23 * ADLink ACL-8112DG/HG/PG, ACL-8113, ACL-8216,
24 * ICP DAS A-821PGH/PGL/PGL-NDA, A-822PGH/PGL, A-823PGH/PGL, A-826PG,
25 * ICP DAS ISO-813
[all …]
/openbmc/linux/drivers/net/wwan/t7xx/
H A Dt7xx_netdev.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2021-2022, Intel Corporation.
27 #include <linux/list.h>
49 struct dpmaif_ctrl *ctrl; in t7xx_ccmni_enable_napi() local
52 ctrl = ctlb->hif_ctrl; in t7xx_ccmni_enable_napi()
54 if (ctlb->is_napi_en) in t7xx_ccmni_enable_napi()
62 ret = pm_runtime_resume_and_get(ctrl->dev); in t7xx_ccmni_enable_napi()
64 dev_err(ctrl->dev, "Failed to resume device: %d\n", in t7xx_ccmni_enable_napi()
68 napi_enable(ctlb->napi[i]); in t7xx_ccmni_enable_napi()
69 napi_schedule(ctlb->napi[i]); in t7xx_ccmni_enable_napi()
[all …]
/openbmc/linux/drivers/media/pci/saa7134/
H A Dsaa7134-video.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * (c) 2001-03 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
11 #include "saa7134-reg.h"
14 #include <linux/list.h>
20 #include <media/v4l2-common.h>
21 #include <media/v4l2-event.h>
24 /* ------------------------------------------------------------------ */
31 static char secam[] = "--";
35 MODULE_PARM_DESC(gbuffers,"number of capture buffers, range 2-32");
47 /* ------------------------------------------------------------------ */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwcd9335.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
18 #include <sound/soc-dapm.h>
25 #include "wcd-clsh-v2.h"
27 #include <dt-bindings/sound/qcom,wcd9335.h>
98 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
125 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
126 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
127 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
[all …]
H A Dwcd934x.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
21 #include <sound/soc-dapm.h>
23 #include "wcd-clsh-v2.h"
24 #include "wcd-mbhc-v2.h"
187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi11 * notice, this list of conditions and the following disclaimer.
13 * notice, this list of conditions and the following disclaimer in
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_gfx_if.h46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
108 /* PSP boot config sub-commands */
165 …uint32_t num_desc; /* number of buffer descriptors in the list */
166 …uint32_t total_size; /* total size of all buffers in the list in b…
167 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
177 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
190 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi11 * notice, this list of conditions and the following disclaimer.
13 * notice, this list of conditions and the following disclaimer in
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/clock/sun8i-tcon-top.h>
34 if (!sun8i_tcon_top_node_is_tcon_top(dev->of_node)) { in sun8i_tcon_top_set_hdmi_src()
36 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
41 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
44 spin_lock_irqsave(&tcon_top->reg_lock, flags); in sun8i_tcon_top_set_hdmi_src()
46 val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG); in sun8i_tcon_top_set_hdmi_src()
48 val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, tcon - 1); in sun8i_tcon_top_set_hdmi_src()
49 writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG); in sun8i_tcon_top_set_hdmi_src()
51 spin_unlock_irqrestore(&tcon_top->reg_lock, flags); in sun8i_tcon_top_set_hdmi_src()
[all …]

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