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12

/openbmc/u-boot/arch/arm/dts/
H A Domap-gpmc-smsc9221.dtsi13 vddvario: regulator-vddvario {
14 compatible = "regulator-fixed";
15 regulator-name = "vddvario";
16 regulator-always-on;
19 vdd33a: regulator-vdd33a {
20 compatible = "regulator-fixed";
21 regulator-name = "vdd33a";
22 regulator-always-on;
29 bank-width = <2>;
31 gpmc,mux-add-data;
[all …]
H A Domap3-igep.dtsi11 /dts-v1/;
22 stdout-path = &uart3;
26 compatible = "ti,omap-twl4030";
31 vdd33: regulator-vdd33 {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd33";
34 regulator-always-on;
41 pinctrl-single,pins = <
48 pinctrl-single,pins = <
55 pinctrl-single,pins = <
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/openbmc/docs/designs/
H A Duart-mux-support.md1 # uart-mux-support design
12 Some hardware configurations feature a UART mux which can be switched via GPIOs.
13 To support this configuration, obmc-console needs to provide a method for
18 There are already [open changes for obmc-console][obmc-console-uart-mux-series]
21 [obmc-console-uart-mux-series]:
22 https://gerrit.openbmc.org/c/openbmc/obmc-console/+/71864
25 subprojects - not in the way of causing regression, but later when the mentioned
30 - The user can select a console to be muxed
32 - Platform policy (whichever service implements it) can select the appropriate
35 - It is clear to whoever is reading the logs of that console when a console was
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/openbmc/qemu/qapi/
H A Dchar.json1 # -*- Mode: Python -*-
22 # @frontend-open: shows whether the frontend device attached to this
32 'data': { 'label': 'str',
34 'frontend-open': 'bool' } }
37 # @query-chardev:
43 # .. qmp-example::
45 # -> { "execute": "query-chardev" }
46 # <- {
51 # "frontend-open": false
56 # "frontend-open": true
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/openbmc/qemu/tests/unit/
H A Dtest-char.c5 #include "qemu/config-file.h"
9 #include "chardev/char-fe.h"
12 #include "qapi/qapi-commands-char.h"
14 #include "qom/qom-qobject.h"
15 #include "io/channel-socket.h"
16 #include "qapi/qobject-input-visitor.h"
17 #include "qapi/qapi-visit-sockets.h"
18 #include "socket-helpers.h"
43 return sizeof(h->read_buf) - h->read_count; in fe_can_read()
52 memcpy(h->read_buf + h->read_count, buf, size); in fe_read()
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/openbmc/qemu/chardev/
H A Dchar.c4 * Copyright (c) 2003-2008 Fabrice Bellard
28 #include "monitor/qmp-helpers.h"
29 #include "qemu/config-file.h"
30 #include "qemu/error-report.h"
31 #include "qemu/qemu-print.h"
34 #include "qapi/qapi-commands-char.h"
44 #include "chardev-internal.h"
56 CharBackend *be = s->be; in chr_be_event()
58 if (!be || !be->chr_event) { in chr_be_event()
62 be->chr_event(be->opaque, event); in chr_be_event()
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/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
41 * Function to simply acknowledge and propagate changes in a clock mux
46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) in clock_mux_update() argument
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H A Dtrace-events3 # allwinner-cpucfg.c
5 allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%…
6 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x…
8 # allwinner-h3-dramc.c
11 …lwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 "…
12 …inner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 "…
13 …lwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 "…
14 …inner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 "…
15 …lwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 "…
16 …inner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 "…
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/openbmc/openbmc/meta-phosphor/scripts/
H A Drun-repotest1 #!/bin/bash -e
11 # meta-phosphor is also included such that patches that the community agrees to
18 git ls-files -- \
21 ':!:meta-arm/**' \
22 ':!:meta-security/**' \
23 ':!:meta-raspberrypi/**' \
24 ':!:meta-openembedded/**' \
25 ':!:meta-phosphor/**' \
35 # https://github.com/openbmc/docs/blob/master/meta-layer-guidelines.md
37 meta-aspeed/recipes-aspeed/python/socsec/0001-otptool-Define-value_start-in-rev_id-path.patch
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/openbmc/qemu/hw/arm/
H A Daspeed.c9 * the COPYING file in the top-level directory.
26 #include "hw/qdev-properties.h"
27 #include "system/block-backend.h"
30 #include "qemu/error-report.h"
33 #include "hw/qdev-clock.h"
37 .board_id = -1, /* device-tree-only board */
54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
167 /* Quanta-Q71l hardware value */
208 /* Qualcomm DC-SCM hardware value */
226 * r2 = per-cpu go sign value in aspeed_write_smpboot()
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H A Dversatilepb.c4 * Copyright (c) 2005-2007 CodeSourcery.
24 #include "qemu/error-report.h"
29 #include "target/arm/cpu-qom.h"
68 flags = s->level & s->mask; in vpb_sic_update()
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
79 if (!(s->pic_enable & mask)) in vpb_sic_update_pic()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
89 s->level |= 1u << irq; in vpb_sic_set_irq()
91 s->level &= ~(1u << irq); in vpb_sic_set_irq()
92 if (s->pic_enable & (1u << irq)) in vpb_sic_set_irq()
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/openbmc/qemu/
H A Dqemu-options.hx14 "-h or -help display this help and exit\n", QEMU_ARCH_ALL)
16 ``-h``
21 "-version display version information and exit\n", QEMU_ARCH_ALL)
23 ``-version``
28 "-machine [type=]name[,prop[=value][,...]]\n"
29 " selects emulated machine ('-machine help' for list)\n"
33 " dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
34 " mem-merge=on|off controls memory merge support (default: on)\n"
35 " aes-key-wrap=on|off controls support for AES key wrapping (default=on)\n"
36 " dea-key-wrap=on|off controls support for DEA key wrapping (default=on)\n"
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/openbmc/intel-ipmi-oem/
H A Dipmi-allowlist.conf34 0x04:0x2a:0x7f7f //<Sensor/Event>:<Re-arm Sensor Events>
94 0x08:0x25:0xf93e //<Firmware>:<Get Boot Certificate Data>
106 0x0a:0x11:0xff7f //<Storage>:<Read FRU Data>
107 0x0a:0x12:0x7f7f //<Storage>:<Write FRU Data>
112 0x0a:0x24:0x7f7f //<Storage>:<Add SDR>
113 0x0a:0x25:0x7f7f //<Storage>:<Partial Add SDR>
122 0x0a:0x44:0x7f7f //<Storage>:<Add SEL Entry>
123 0x0a:0x45:0x7f7f //<Storage>:<Add Partial SEL Entry>
138 0x0c:0x12:0x7f7f //<Transport>:<SM SetSerial Modem Mux>
139 0x0c:0x14:0x7f7f //<Transport>:<Set PPP UDP Proxy Transmit Data>
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/openbmc/s2600wf-misc/subprojects/hsbp-manager/src/
H A Dhsbp_manager.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
41 #include <linux/i2c-dev.h>
97 rootBus = -1; in clearConfig()
116 int file = -1;
130 file = open(("/dev/i2c-" + std::to_string(bus)).c_str(), in initialize()
135 << "\" - Unable to open bus : " << bus << "\n"; in initialize()
143 << "\" - Unable to set address to " << address in initialize()
156 << "\" - Byte map error ! Unable to find " in initialize()
167 << "\" - Error: Unable to read data from clock " in initialize()
176 * ignore where byteMap is "-"). We do not want to touch other in initialize()
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/openbmc/s2600wf-misc/hsbp-manager/src/
H A Dhsbp_manager.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
41 #include <linux/i2c-dev.h>
97 rootBus = -1; in clearConfig()
116 int file = -1;
130 file = open(("/dev/i2c-" + std::to_string(bus)).c_str(), in initialize()
135 << "\" - Unable to open bus : " << bus << "\n"; in initialize()
143 << "\" - Unable to set address to " << address in initialize()
156 << "\" - Byte map error ! Unable to find " in initialize()
167 << "\" - Error: Unable to read data from clock " in initialize()
176 * ignore where byteMap is "-"). We do not want to touch other in initialize()
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
19 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
73 u32 data; in polling_with_timeout() local
77 data = readl(addr) & mask; in polling_with_timeout()
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
81 return data; in polling_with_timeout()
90 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
102 * U-Boot to mainline version. in comphy_pcie_power_up()
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/openbmc/u-boot/env/
H A DKconfig20 while U-Boot is running, but once U-Boot exits it will not be
21 stored. U-Boot will therefore always start up with a default
31 - CONFIG_ENV_OFFSET:
32 - CONFIG_ENV_SIZE:
41 - CONFIG_ENV_EEPROM_IS_ON_I2C
45 - CONFIG_I2C_ENV_EEPROM_BUS
53 a pca9547 i2c mux with address 0x70, channel 3.
88 "embedded" in the text segment with the U-Boot code. This
94 4 kB sectors - with U-Boot code before and after it. With
97 between U-Boot and the environment.
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 adr r0, reset /* r0 <- Runtime value of reset */
50 ldr r1, =reset /* r1 <- Linked value of reset */
51 subs r4, r0, r1 /* r4 <- Run-vs-link offset */
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/openbmc/u-boot/include/
H A Dec_commands.h2 * Use of this source code is governed by a BSD-style license that can be
18 * - CMD is the command code. (defined by EC_CMD_ constants)
19 * - ERR is the error code. (defined by EC_RES_ constants)
20 * - Px is the optional payload.
23 * - S is the checksum which is the sum of all payload bytes.
59 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
66 #define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
78 /* The offset address of each type of data in mapped memory. */
79 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
80 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
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/openbmc/u-boot/board/freescale/m5373evb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m5373evb/m5373evb.c Dram setup
13 - board/freescale/m5373evb/mii.c Mii access
14 - board/freescale/m5373evb/Makefile Makefile
15 - board/freescale/m5373evb/config.mk config make
16 - board/freescale/m5373evb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf532x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
20 - arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
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/openbmc/obmc-console/
H A Dconsole-server.c10 * http://www.apache.org/licenses/LICENSE-2.0
41 #include "console-mux.h"
43 #include "console-server.h"
60 " --config <FILE>\tUse FILE for configuration\n" in usage()
61 " --console-id <NAME>\tUse NAME in the UNIX domain socket address\n" in usage()
68 return p->fd == -1 && p->events == 0 && p->revents == ~0; in console_server_pollfd_reclaimable()
74 for (size_t i = 0; i < server->capacity_pollfds; i++) { in console_server_find_released_pollfd()
75 struct pollfd *p = &server->pollfds[i]; in console_server_find_released_pollfd()
80 return -1; in console_server_find_released_pollfd()
83 // returns the index of that pollfd in server->pollfds
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/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
44 * However, to support simulation-time selection of fast simulation mode, where
47 * check, which is based on the rtl-supplied value, or we dynamically compute
48 * the value to use based on the dynamically-chosen calibration mode
64 * non-skip and skip values
66 * The mask is set to include all bits when not-skipping, but is
70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage()
86 gbl->error_substage = substage; in set_failing_group_stage()
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/openbmc/u-boot/
H A DREADME1 # SPDX-License-Identifier: GPL-2.0+
3 # (C) Copyright 2000 - 2013
9 This directory contains the source code for U-Boot, a boot loader for
15 The development of U-Boot is closely related to Linux: some parts of
23 add new commands. Also, instead of permanently adding rarely used
37 scattered throughout the U-Boot source identifying the people or
41 actual U-Boot source tree; however, it can be created dynamically
51 U-Boot, you should send a message to the U-Boot mailing list at
52 <u-boot@lists.denx.de>. There is also an archive of previous traffic
53 on the mailing list - please search the archive before asking FAQ's.
[all …]
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
346 /* Per-port registers */
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
393 * relative to port->base.
491 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
493 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
495 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
[all …]

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