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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml7 title: MTK MSDC Storage Host Controller
58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
65 - const: msdc
247 - description: msdc subsys clock gate
291 - description: msdc subsys clock gate
338 interrupt-names = "msdc", "sdio_wakeup";
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623n-bananapi-bpi-r2.dts126 function = "msdc";
151 function = "msdc";
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192-msdc.c61 .name = "clk-mt8192-msdc",
H A DKconfig838 tristate "Clock driver for MediaTek MT8192 msdc"
842 This driver supports MediaTek MT8192 msdc and msdc_top clocks.
H A DMakefile125 obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
/openbmc/linux/drivers/mmc/host/
H A Dmtk-sd.c448 struct clk *src_clk; /* msdc source clock */
449 struct clk *h_clk; /* msdc h_clk */
451 struct clk *src_clk_cg; /* msdc source clock control gate */
452 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
453 struct clk *crypto_clk; /* msdc crypto clock control gate */
2203 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2460 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL in msdc_cqe_cit_cal()
3043 .name = "mtk-msdc",
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8192-clk.h412 /* MSDC */
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7623.c673 /* MSDC */
1222 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7623.c812 /* MSDC */
1353 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
/openbmc/u-boot/drivers/mmc/
H A Dmtk-sd.c250 struct clk h_clk; /* MSDC core clock */
/openbmc/linux/fs/ceph/
H A Dsuper.h401 * or msdc->cap_dirty_lock. List presence can also be checked while
/openbmc/linux/
H A Dopengrok1.0.log[all...]