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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpm8841.dtsi44 pm8841_mpps: mpps@a000 {
H A Dpma8084.dtsi40 pma8084_mpps: mpps@a000 {
H A Dpm8226.dtsi143 pm8226_mpps: mpps@a000 {
H A Dpm8941.dtsi120 pm8941_mpps: mpps@a000 {
H A Dqcom-mdm9615.dtsi282 pm8018_mpps: mpps@50 {
H A Dqcom-msm8660.dtsi363 pm8058_mpps: mpps@50 {
H A Dqcom-apq8064.dtsi672 pm8821_mpps: mpps@50 {
711 pm8921_mpps: mpps@50 {
H A Dqcom-apq8060-dragonboard.dts433 dragon_cm3605_mpps: cm3605-mpps-state {
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8994.dtsi23 pmi8994_mpps: mpps@a000 {
H A Dpmi8950.dtsi60 pmi8950_mpps: mpps@a000 {
H A Dpm8994.dtsi121 pm8994_mpps: mpps@a000 {
H A Dpm8950.dtsi147 pm8950_mpps: mpps@a000 {
H A Dpm8916.dtsi101 pm8916_mpps: mpps@a000 {
H A Dapq8016-sbc.dts700 pm8916_mpps_leds: pm8916-mpps-state {
H A Dmsm8996-sony-xperia-tone.dtsi438 pm8994_mpps_defaults: pm8994-mpps-default-state {
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.c281 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b in cx18_av_std_setup()
341 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is in cx18_av_std_setup()
343 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after in cx18_av_std_setup()
355 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks in cx18_av_std_setup()
401 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is in cx18_av_std_setup()
403 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the in cx18_av_std_setup()
417 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks in cx18_av_std_setup()
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-cp110.c24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
H A Dpinctrl-dove.c268 * break other functions. If you require all mpps as gpio
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,pmic-mpp.yaml161 pm8841_mpp: mpps@a000 {
/openbmc/u-boot/include/configs/
H A Dedminiv2.h42 * - MPPs 12 to 15 are SATA LEDs (mode 5)
/openbmc/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c32 * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dcpu.c274 /* Set CPIOs and MPPs - values provided by board in arch_misc_init()
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,spmi-pmic.yaml183 "^mpps@[0-9a-f]+$":
/openbmc/linux/Documentation/networking/
H A Dpktgen.rst228 pgset "ratep 1000000" set rate to 1Mpps
/openbmc/linux/drivers/iio/adc/
H A Dqcom-pm8xxx-xoadc.c288 * matrix where they can be routed to any of the MPPs, not just

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