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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dreboot-mode.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic reboot mode core map
10 - Andy Yan <andy.yan@rock-chips.com>
13 This driver get reboot mode arguments and call the write
15 or ram. Then the bootloader can read it and take different
18 All mode properties are vendor specific, it is a indication to tell
19 the bootloader what to do when the system reboots, and should be named
[all …]
H A Dnvmem-reboot-mode.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/nvmem-reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic NVMEM reboot mode
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
13 This driver gets the reboot mode magic value from the reboot-mode driver
14 and stores it in the NVMEM cell named "reboot-mode". The bootloader can
19 const: nvmem-reboot-mode
21 nvmem-cells:
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H A Dsyscon-reboot-mode.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON reboot mode driver
10 - Sebastian Reichel <sre@kernel.org>
13 This driver gets reboot mode magic value from reboot-mode driver
14 and stores it in a SYSCON mapped register. Then the bootloader
17 parental dt-node plus the offset. So the SYSCON reboot-mode node
18 should be represented as a sub-node of a "syscon", "simple-mfd" node.
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A DREADME2 -----
3 The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single
4 disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same.
5 The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore
6 the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell
7 88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the
8 bootloader and its environment. The linux kernel and the initial ramdisk
12 Rescue Mode
13 -----------
19 Therefore, on entering the resuce mode, a random ethernet address is
[all …]
/openbmc/u-boot/tools/
H A Dublimage.h1 /* SPDX-License-Identifier: GPL-2.0+ */
25 CFG_INVALID = -1,
35 /* Safe boot mode */
37 /* DMA boot mode */
39 /* I Cache boot mode */
41 /* Fast EMIF boot mode */
43 /* DMA + ICache boot mode */
45 /* DMA + ICache + Fast EMIF boot mode */
57 uint32_t entry; /* entry point address for bootloader */
58 uint32_t pages; /* number of pages (size of bootloader) */
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/openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dcypress,cy8ctma340.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Javier Martinez Canillas <javier@dowhile0.org>
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: touchscreen.yaml#
26 - const: cypress,cy8ctma340
27 - const: cypress,cy8ctst341
28 - const: cypress,cyttsp-spi
31 - const: cypress,cyttsp-i2c
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/openbmc/u-boot/doc/
H A DREADME.ramboot-ppc85xx5 pre-mechanism is required to load the DDR with the bootloader binary.
6 - In case of SD and SPI boot this is done by BootROM code inside the chip
8 - In case of NAND boot FCM supports loading initial 4K code from NAND flash
9 which can initialize the DDR and get the complete bootloader copied to DDR.
15 1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
16 execute the bootloader from DDR.
18 - In very early stage of platform bringup where other boot options are not
20 - In case the support to program the flashes on the board is not available.
22 2. Load the RAM based bootloader onto DDR using already existing bootloader on
23 the board.And then execute the bootloader from DDR.
[all …]
H A DREADME.ublimage1 ---------------------------------------------
3 ---------------------------------------------
5 This document describes how to set up an U-Boot image that can be directly
6 booted by a DaVinci processor via NAND boot mode, using an UBL header,
13 --------------
14 ./tools/mkimage -l <u-boot_file>
17 ./tools/mkimage -T ublimage \
18 -n <board specific configuration file> \
19 -d <u-boot binary> <output image file>
22 ./tools/mkimage -n ./board/davinci/dm365evm/ublimage.cfg \
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/openbmc/linux/drivers/usb/typec/ucsi/
H A Ducsi_stm32g0.c1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 * UCSI driver for STMicroelectronics STM32G0 Type-C PD controller
5 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
19 /* STM32G0 I2C bootloader addr: 0b1010001x (See AN2606) */
22 /* STM32G0 I2C bootloader max data size */
25 /* STM32 I2C bootloader commands (See AN4221) */
26 #define STM32_CMD_GVR 0x01 /* Gets the bootloader version */
33 #define STM32_CMD_GLOBAL_MASS_ERASE 0xffff /* All-bank erase */
35 /* STM32 I2C bootloader answer status */
50 #define STM32G0_FW_RSTGOBL 0x21 /* Reset and go to bootloader */
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/openbmc/linux/arch/arm64/include/asm/
H A Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * The hypercall is allowed to clobber any of the caller-saved
17 * registers (x0-x18), so it is advisable to use it through the
18 * indirection of a function call (as implemented in hyp-stub.S).
22 * HVC_SET_VECTORS - Set the value of the vbar_el2 register.
29 * HVC_SOFT_RESTART - CPU soft reset, used by the cpu_soft_restart routine.
34 * HVC_RESET_VECTORS - Restore the vectors to the original HYP stubs
39 * HVC_FINALISE_EL2 - Upgrade the CPU from EL1 to EL2, if possible
53 * Flags returned together with the boot mode, but not preserved in
67 * __boot_cpu_mode records what mode CPUs were booted in.
[all …]
/openbmc/linux/arch/arm/include/asm/
H A Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Flag indicating that the kernel was not entered in the same mode on every
23 * __boot_cpu_mode records what mode the primary CPU was booted in.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
26 * that some CPU(s) were booted in a different mode.
50 /* Reports the availability of HYP mode */
57 /* Check if the bootloader has booted CPUs in different modes */
/openbmc/linux/arch/arm/mach-exynos/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/platform_data/cpuidle-exynos.h>
113 /* CPU BOOT mode flag for Exynos3250 SoC bootloader */
116 * Magic values for bootloader indicating chosen low power mode.
117 * See also Documentation/arch/arm/samsung/bootloader-interface.rst
123 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
124 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
/openbmc/linux/drivers/input/mouse/
H A Dcyapa_gen3.c9 * Copyright (C) 2011-2015 Cypress Semiconductor, Inc.
10 * Copyright (C) 2011-2012 Google, Inc.
60 * Used in register 0x00, bit1-0, DeviceStatus field.
88 * bit 7 - 4: high 4 bits of x position value
89 * bit 3 - 0: high 4 bits of y position value
95 /* id range is 1 - 15. It is incremented with every new touch. */
101 * bit 0 - 1: device status
102 * bit 3 - 2: power mode
103 * bit 6 - 4: reserved
108 * bit 7 - 4: number of fingers currently touching pad
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d27_wlsom1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
11 #include "sama5d2-pinfunc.h"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/pinctrl/at91.h>
18 compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
26 clock-frequency = <32768>;
30 clock-frequency = <24000000>;
35 compatible = "mmc-pwrseq-wilc1000";
[all …]
H A Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 compatible = "atmel,tcb-timer";
44 compatible = "atmel,tcb-timer";
51 pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
52 pinctr-name = "default";
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5200b.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&mpc5200_pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
26 d-cache-line-size = <32>;
27 i-cache-line-size = <32>;
28 d-cache-size = <0x4000>; // L1, 16K
[all …]
/openbmc/linux/drivers/bluetooth/
H A Dbtintel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
66 if (skb->len != sizeof(*bda)) { in btintel_check_bdaddr()
69 return -EIO; in btintel_check_bdaddr()
72 bda = (struct hci_rp_read_bd_addr *)skb->data; in btintel_check_bdaddr()
79 if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) { in btintel_check_bdaddr()
81 &bda->bdaddr); in btintel_check_bdaddr()
82 set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); in btintel_check_bdaddr()
98 bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)", in btintel_enter_mfg()
114 * 0x00: Just disable the manufacturing mode (0x00). in btintel_exit_mfg()
115 * 0x01: Disable manufacturing mode and reset with patches deactivated. in btintel_exit_mfg()
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dmelfas_mip4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
185 .addr = ts->client->addr, in mip4_i2c_xfer()
190 .addr = ts->client->addr, in mip4_i2c_xfer()
201 res = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg)); in mip4_i2c_xfer()
205 error = res < 0 ? res : -EIO; in mip4_i2c_xfer()
206 dev_err(&ts->client->dev, in mip4_i2c_xfer()
207 "%s - i2c_transfer failed: %d (%d)\n", in mip4_i2c_xfer()
209 } while (--retry); in mip4_i2c_xfer()
216 v->boot = get_unaligned_le16(buf + 0); in mip4_parse_fw_version()
217 v->core = get_unaligned_le16(buf + 2); in mip4_parse_fw_version()
[all …]
/openbmc/u-boot/board/gateworks/gw_ventana/
H A DREADME1 U-Boot for the Gateworks Ventana Product Family boards
3 This file contains information for the port of U-Boot to the Gateworks
7 is supported by a single bootloader build by using a common SPL and U-Boot
13 ---------------------------------
19 will build the following artifacts from U-Boot source:
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
22 The DRAM controller, loads u-boot.img from the detected boot device,
25 - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
29 --------
31 To build U-Boot for the Gateworks Ventana product family:
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * Note: this Device Tree assumes that the bootloader has remapped the
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
16 * boards were delivered with an older version of the bootloader that
18 * situation, you should either update your bootloader (preferred
22 /dts-v1/;
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-sysinfo.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * This module provides system/board information obtained by the bootloader.
35 #include "cvmx-coremask.h"
46 * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is
71 /* exception base address, as set by bootloader */
93 * proper addressing mode (XKPHYS, KSEG0, etc.)
101 * application to use the proper addressing mode (XKPHYS,
107 /* configuration flags from bootloader */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xcm.dtsi2 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
15 stdout-path = "serial0:115200n8";
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
35 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 phy-mode = "rgmii";
40 #address-cells = <1>;
41 #size-cells = <0>;
43 ethernet-phy@1 {
45 interrupt-parent = <&pioB>;
[all …]
/openbmc/u-boot/include/
H A Dvxworks.h1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * VxWorks on x86 gets E820 information from pre-defined offset @
31 * later for sanity test during the kernel boot-up.
36 /* E820 info signatiure "SMAP" - System MAP */
51 * VxWorks bootloader stores its size at a pre-defined offset @ 0x5004.
53 * retrieved from the E820 table, the bootloader size will be subtracted
60 * When booting from EFI BIOS, VxWorks bootloader stores the EFI GOP
61 * framebuffer info at a pre-defined offset @ 0x6100. When VxWorks kernel
67 * EFI console driver to function (eg: EFI loader in U-Boot). If U-Boot has
68 * already initialized the graphics card and set it to a VESA mode that is
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dti_qspi.txt4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
6 - reg-names: Should contain the resource reg names.
7 - qspi_base: Qspi configuration register Address space
8 - qspi_mmap: Memory mapped Address space
9 - (optional) qspi_ctrlmod: Control module Address space
10 - interrupts: should contain the qspi interrupt number.
11 - #address-cells, #size-cells : Must be present if the device has sub-nodes
12 - ti,hwmods: Name of the hwmod associated to the QSPI
15 - spi-max-frequency: Definition as per
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dreal2.S14 #include <asm/asm-offsets.h>
32 /************************ 32-bit real-mode calls ***********************/
46 STREG %rp, -RP_OFFSET(%sp) /* save RP */
50 STREG %r27, -1*REG_SZ(%sp)
51 STREG %r29, -2*REG_SZ(%sp)
53 STREG %sp, -REG_SZ(%arg0) /* save SP on real-mode stack */
54 copy %arg0, %sp /* adopt the real-mode SP */
60 /* 32-bit calling convention passes first 4 args in registers */
62 ldw -8(%arg1), %arg2
63 ldw -12(%arg1), %arg3
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