Home
last modified time | relevance | path

Searched +full:mipi +full:- +full:dsi1 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
[all …]
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt36523.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...) \ argument
29 mipi_dsi_dcs_write_seq(dsi1, cmd, seq); \
70 struct mipi_dsi_device *dsi0 = pinfo->dsi[0]; in elish_boe_init_sequence()
71 struct mipi_dsi_device *dsi1 = pinfo->dsi[1]; in elish_boe_init_sequence() local
73 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
74 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
75 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05); in elish_boe_init_sequence()
76 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20); in elish_boe_init_sequence()
77 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
4 The MIPI Display Serial Interface specifies a serial bus and a protocol for
8 This document describes DSI bus-specific properties only or defines existing
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
29 - #size-cells: Should be 0. There are cases where it makes sense to use a
33 - clock-master: boolean. Should be enabled if the host is being used in
43 ------------------------------------------------------
49 device-specific properties.
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
[all …]
/openbmc/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
51 * which is used to control the reset for the MIPI Phy.
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
44 struct mipi_dsi_device *dsi1; member
102 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
103 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
106 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
121 if (lt9611->dsi1_node) in lt9611_mipi_input_digital()
124 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
31 /* -----------------------------------------------------------------------------
283 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
513 /* R8A779A0 has two MIPI DSI outputs. */
534 /* R8A779G0 has two MIPI DSI outputs. */
549 { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
550 { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
109 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
125 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
[all …]
H A Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
111 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dicl_dsi.c71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
108 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
115 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
118 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
121 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
126 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
[all …]
H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
47 #include <media/cec-notifier.h>
69 /* these are outputs from the chip - integrated only
87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
103 * create the DMA scatter-gather list for each FB color plane. This sg
115 * in the rotated and remapped GTT view all no-CCS formats (up to 2
206 * state. This must be called _after_ display->get_pipe_config has
207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
349 /* MIPI DSI */
422 * and the bus-specific code. What that means is that HDCP over HDMI differs
[all …]
/openbmc/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]