microcode (full) in projects: openbmc - OpenGrok search results

Searched full:microcode (Results 1 – 25 of 482) sorted by relevance

/openbmc/u-boot/tools/binman/etype/
H A D	u_boot_ucode.py	5 # Entry-type module for a U-Boot binary with an embedded microcode pointer 13 """U-Boot microcode block 21 U-Boot on x86 needs a single block of microcode. This is collected from 22 the various microcode update nodes in the device tree. It is also unable 23 to read the microcode from the device tree on platforms that use FSP 25 microcode is supplied before there is any SRAM available to use (i.e. 27 requires the microcode!). To keep things simple, all x86 platforms handle 28 microcode the same way in U-Boot (even non-FSP platforms). This is that 30 size of the microcode. This is either passed to the FSP (for FSP 31 platforms), or used to set up the microcode (for non-FSP platforms). [all …]
H A D	u_boot_with_ucode_ptr.py	5 # Entry-type module for a U-Boot binary with an embedded microcode pointer 18 """U-Boot with embedded microcode pointer 22 - optional-ucode: boolean property to make microcode optional. If the 23 u-boot.bin image does not include microcode, no error will 28 microcode, to allow early x86 boot code to find it without doing anything 40 # Figure out where to put the microcode pointer 50 # If the image does not need microcode, there is nothing to do 54 # Get the offset of the microcode 57 self.Raise('Cannot find microcode region u-boot-ucode') 71 …self.Raise('Microcode pointer _dt_ucode_base_size at %08x is outside the section ranging from %08x… [all …]
H A D	u_boot_dtb_with_ucode.py	5 # Entry-type module for U-Boot device tree with the microcode removed 14 """A U-Boot device tree file, with the microcode removed 21 contains the microcode. If the microcode is not being collated into one 22 place then the offset and size of the microcode is recorded by this entry, 24 entry deletes the microcode from the device tree (to save space) and makes 43 # If the section does not need microcode, there is nothing to do 55 # Remove the microcode 58 self.ucode = fdt.GetNode('/microcode') 60 raise self.Raise("No /microcode node found in '%s'" % fname) 62 # There's no need to collate it (move all microcode into one place) [all …]
/openbmc/linux/Documentation/arch/x86/
H A D	microcode.rst	4 The Linux Microcode Loader 11 The kernel has a x86 microcode loading facility which is supposed to 12 provide microcode loading methods in the OS. Potential use cases are 13 updating the microcode on platforms beyond the OEM End-Of-Life support, 14 and updating the microcode on long-running systems without rebooting. 18 Early load microcode 21 The kernel can update microcode very early during boot. Loading 22 microcode early can fix CPU issues before they are observed during 25 The microcode is stored in an initrd file. During boot, it is read from 28 The format of the combined initrd image is microcode in (uncompressed) [all …]
/openbmc/u-boot/tools/
H A D	microcode-tool.py	6 # Intel microcode update tool 14 MICROCODE_DIR = 'arch/x86/dts/microcode' 16 class Microcode: class 17 """Holds information about the microcode for a particular model of CPU. 20 name: Name of the CPU this microcode is for, including any version 23 words: List of hex words containing the microcode. The first 16 words 47 microcodes: List of Microcode objects from the file 65 microcodes[name] = Microcode(name, data) 75 microcodes[name] = Microcode(name, data) 86 microcodes: List of Microcode objects from the file [all …]
H A D	microcode-tool	6 # Intel microcode update tool 14 MICROCODE_DIR = 'arch/x86/dts/microcode' 16 class Microcode: class 17 """Holds information about the microcode for a particular model of CPU. 20 name: Name of the CPU this microcode is for, including any version 23 words: List of hex words containing the microcode. The first 16 words 47 microcodes: List of Microcode objects from the file 65 microcodes[name] = Microcode(name, data) 75 microcodes[name] = Microcode(name, data) 86 microcodes: List of Microcode objects from the file [all …]
/openbmc/linux/Documentation/powerpc/
H A D	qe_firmware.rst	12 II - Microcode Availability 16 IV - Microcode Programming Details 34 II - Microcode Availability 44 In this document, the term 'microcode' refers to the sequence of 32-bit 45 integers that compose the actual QE microcode. 47 The term 'firmware' refers to a binary blob that contains the microcode as 50 1) describes the microcode's purpose 51 2) describes how and where to upload the microcode 57 IV - Microcode Programming Details 60 The QE architecture allows for only one microcode present in I-RAM for each [all …]
/openbmc/linux/Documentation/power/
H A D	suspend-and-cpuhotplug.rst	176 There are some interesting situations involving CPU hotplug and microcode 179 [Please bear in mind that the kernel requests the microcode images from 187 to apply the same microcode revision to each of the CPUs. 190 and thereby in applying the correct microcode revision to it. 191 But note that the kernel does not maintain a common microcode image for the 197 In this case since we probably need to apply different microcode revisions 198 to different CPUs, the kernel maintains a copy of the correct microcode 208 (which is sent by the CPU hotplug code), the microcode update driver's 210 microcode image for that CPU. 213 doesn't have the microcode image, it does the CPU type/model discovery [all …]
/openbmc/linux/arch/x86/kernel/cpu/microcode/
H A D	core.c	3 * CPU Microcode Update Driver for Linux 9 * X86 CPU microcode early update for Linux: 15 * This driver allows to upgrade microcode on x86 processors. 18 #define pr_fmt(fmt) "microcode: " fmt 255 * is loading microcode in order to avoid any negative interactions caused by in find_microcode_in_initrd() 258 * - In addition, microcode update on the cores must be serialized until this in find_microcode_in_initrd() 353 panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); in check_online_cpus() 508 * while the primary thread updates the microcode. Instrumentation can end in version_show() 513 * microcode update handles this correctly. It's only the sibling code in version_show() 543 int old_rev = boot_cpu_data.microcode; [all...]
H A D	intel.c	3 * Intel CPU Microcode Update Driver for Linux 8 * Intel CPU microcode early update for Linux 13 #define pr_fmt(fmt) "microcode: " fmt 32 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; 36 /* Current microcode patch used in early patching on the APs. / 43 / microcode format is extended from prescott processors / 124 intel_microcode_sanity_check() - Sanity check microcode file. in intel_find_matching_signature() 125 * @mc: Pointer to the microcode file contents. in intel_find_matching_signature() 127 * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. 128 * Validate if the microcode heade [all...]
H A D	Makefile	`2 microcode-y := core.o 3 obj-$(CONFIG_MICROCODE) += microcode.o 4 microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o 5 microcode-$(CONFIG_CPU_SUP_AMD) += amd.o`
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A D	gather_data_sampling.rst	48 This issue is mitigated in microcode. The microcode defines the following new 62 GDS can also be mitigated on systems that don't have updated microcode by 76 use the microcode mitigation when available or disable AVX on affected systems 77 where the microcode hasn't been updated to include the mitigation. 91 Vulnerable: No microcode Processor vulnerable and microcode is missing 94 no microcode Processor is vulnerable and microcode is missing 96 Mitigation: Microcode Processor is vulnerable and mitigation is in 98 Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in 108 The updated microcode will enable the mitigation by default. The kernel's
H A D	srso.rst	36 First of all, it is required that the latest microcode be loaded for 53 * 'Vulnerable: No microcode': 55 The processor is vulnerable, no microcode extending IBPB 58 * 'Vulnerable: Safe RET, no microcode': 61 kernel, but the IBPB-extending microcode has not been applied. User 64 * 'Vulnerable: Microcode, no safe RET': 66 Extended IBPB functionality microcode patch has been applied. It does 83 (spec_rstack_overflow=microcode) 87 Combined microcode/software mitigation. It complements the 88 extended IBPB microcode patch functionality by addressing [all …]
/openbmc/u-boot/drivers/qe/
H A D	qe.c	186 * Upload microcode to IRAM for those SOCs in qe_init() 192 /* enable the microcode in IRAM / in qe_init() 210 Upload microcode to IRAM for those SOCs which do not have ROM in QE. in qe_init() 214 /* enable the microcode in IRAM / in qe_init() 414 Upload a QE microcode 417 * the actual uploading of the microcode. 426 printf("QE: uploading microcode '%s' version %u.%u.%u\n", in qe_upload_microcode() 430 printf("QE: uploading microcode '%s'\n", (char )ucode->id); in qe_upload_microcode() 441 Upload a microcode to the I-RAM at a specific address. 443 * See docs/README.qe_firmware for information on QE microcode uploading. [all …]
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A D	microcode.c	6 * Microcode update for Intel PIII and later CPUs 14 #include <asm/microcode.h> 22 * struct microcode_update - standard microcode header from Intel 66 /* Quark does not have microcode MSRs / in microcode_read_rev() 99 / CPUID sets MSR 0x8B iff a microcode update has been loaded. / in microcode_read_cpu() 116 debug("microcode: sig=%#x pf=%#x revision=%#x\n", in microcode_read_cpu() 121 / Get a microcode update from the device tree and apply it / 148 The microcode has been removed from the device tree in microcode_update_intel() 152 debug("%s: Microcode data not available\n", __func__); in microcode_update_intel() 172 debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", in microcode_update_intel() [all …]
/openbmc/u-boot/arch/x86/include/asm/
H A D	microcode.h	`16 * microcode_update_intel() - Apply microcode updates 18 * Applies any microcode updates in the device tree. 26 * microcode_read_rev() - Read the microcode version 28 * This reads the microcode version of the currently running CPU 30 * @return microcode version number`
/openbmc/u-boot/tools/binman/
H A D	README.entries	150 This file contains microcode for some devices in a special format. An 151 example filename is 'Microcode/C0_22211.BIN'. 360 Entry: u-boot-dtb-with-ucode: A U-Boot device tree file, with the microcode removed 368 contains the microcode. If the microcode is not being collated into one 369 place then the offset and size of the microcode is recorded by this entry, 371 entry deletes the microcode from the device tree (to save space) and makes 496 Entry: u-boot-spl-with-ucode-ptr: U-Boot SPL with embedded microcode pointer 499 This is used when SPL must set up the microcode for U-Boot. 542 Entry: u-boot-tpl-dtb-with-ucode: U-Boot TPL with embedded microcode pointer 545 This is used when TPL must set up the microcode for U-Boot. [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	132 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 136 …is event counts cycles during which the microcode sequencer assisted the Front-end in delivering u… 141 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 149 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) i… 158 … (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 166 …initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 174 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 183 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (M… 186 …s uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assis…
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	132 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 136 …is event counts cycles during which the microcode sequencer assisted the Front-end in delivering u… 141 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 149 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) i… 158 … (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 166 …initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 174 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 183 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (M… 186 …s uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assis…
/openbmc/u-boot/arch/x86/cpu/
H A D	sipi_vector.S	`10 * loads microcode, sets up MSRs, and enables caching before calling into 119 /* Determine if one should check microcode versions / 124 / Get the Microcode version / 133 / Determine if parallel microcode loading is allowed / 137 / Protect microcode loading / 143 / Load new microcode / 148 The microcode pointer is passed in pointing to the header. Adjust 156 /* Unconditionally unlock microcode loading */`
/openbmc/pldm/host-bmc/dbus/
H A D	cpu_core.cpp	`8 uint32_t CPUCore::microcode() const in microcode() function in pldm::dbus::CPUCore 11 microcode(); in microcode() 14 uint32_t CPUCore::microcode(uint32_t value) in microcode() function in pldm::dbus::CPUCore 17 microcode(value); in microcode()`
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	frontend.json	145 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 149 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 154 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 158 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 163 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) i… 168 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) i… 173 … (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 181 …initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 189 …tches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 194 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	145 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 149 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 154 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 158 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 163 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) i… 168 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) i… 173 … (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 181 …initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) i… 189 …tches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 194 …ches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", [all …]
/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A D	Kconfig	`22 In order to use this driver, you will need a microcode (uCode) 23 image for it. You can obtain the microcode from: 27 The microcode is typically installed in /lib/firmware. You can 49 In order to use this driver, you will need a microcode (uCode) 50 image for it. You can obtain the microcode from: 54 The microcode is typically installed in /lib/firmware. You can`
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	128 …s when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 132 …ch uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) i… 137 …uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 141 …r (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) i… 146 …uction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) i… 151 …on Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) i… 156 … (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 159 …B) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) i… 164 …initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) i… 167 …iated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) i… [all …]

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