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/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-ventana.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <70600000>;
44 hback-porch = <58>;
45 hfront-porch = <58>;
46 hsync-len = <58>;
47 vback-porch = <4>;
48 vfront-porch = <4>;
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H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
52 clock-frequency = <100000>;
54 acodec: audio-codec@10 {
57 interrupt-parent = <&gpio>;
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H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
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H A Dtegra20-harmony.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <42430000>;
44 hback-porch = <138>;
45 hfront-porch = <34>;
46 hsync-len = <136>;
47 vback-porch = <21>;
48 vfront-porch = <4>;
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H A Dtegra20-paz00.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uarta;
39 display-timings {
42 clock-frequency = <54030000>;
45 hback-porch = <160>;
46 hfront-porch = <24>;
47 hsync-len = <136>;
48 vback-porch = <3>;
49 vfront-porch = <61>;
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H A Dat91sam9g20ek_common.dtsi2 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
12 u-boot,dm-pre-reloc;
13 stdout-path = &dbgu;
22 clock-frequency = <32768>;
26 clock-frequency = <18432000>;
42 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
50 u-boot,dm-pre-reloc;
55 pinctrl-0 =
70 phy-mode = "rmii";
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H A Drk3399-firefly.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-ddr3-1600.dtsi"
13 model = "Firefly-RK3399 Board";
14 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
17 stdout-path = &uart2;
18 u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
22 compatible = "pwm-backlight";
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H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = &uart2;
22 u-boot,dm-pre-reloc;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
35 compatible = "pwm-backlight";
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H A Dtegra20-seaboard.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
31 stdout-path = &uartd;
47 display-timings {
50 clock-frequency = <70600000>;
53 hback-porch = <58>;
54 hfront-porch = <58>;
55 hsync-len = <58>;
56 vback-porch = <4>;
57 vfront-porch = <4>;
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/openbmc/u-boot/arch/x86/dts/
H A Dchromebook_link.dts1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
4 #include <dt-bindings/sound/azalia.h>
16 compatible = "google,link", "intel,celeron-ivybridge";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "intel,core-gen3";
36 intel,apic-id = <0>;
41 compatible = "intel,core-gen3";
43 intel,apic-id = <1>;
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/openbmc/u-boot/drivers/nvme/
H A Dnvme.h1 /* SPDX-License-Identifier: GPL-2.0+ */
43 __u8 mic; member
532 * accesses. Registers with 64-bit address pointers should be written
610 int instance;
614 int q_depth;
640 int devnum;
641 int lba_shift;
/openbmc/qemu/hw/audio/
H A Dac97.c16 * Contributions after 2012-01-13 are licensed under the terms of the
24 #include "hw/qdev-properties.h"
37 #define SR_VALID_MASK ((1 << 5) - 1)
47 #define CR_VALID_MASK ((1 << 5) - 1)
52 #define GC_VALID_MASK ((1 << 6) - 1)
82 #define GS_VALID_MASK ((1 << 18) - 1)
116 unsigned int bd_valid;
132 int invalid_freq[3];
134 int bup_flag;
180 static void po_callback(void *opaque, int free);
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H A Des1370.c53 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
82 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
86 #define CTRL_XCTL1 0x40000000 /* electret mic bias */
111 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
113 #define STAT_MCCB 0x00000010 /* CCB int pending */
114 #define STAT_UART 0x00000008 /* UART int pending */
115 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
116 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
117 #define STAT_ADC 0x00000001 /* ADC int pending */
119 #define USTAT_RXINT 0x80 /* UART rx int pending */
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) Copyright 2007-2011
99 u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
181 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
206 #define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
207 #define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
208 #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
214 #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
217 #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
222 #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
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/openbmc/u-boot/include/linux/usb/
H A Dch9.h8 * - the master/host side Linux-USB kernel driver API;
9 * - the "usbfs" user space API; and
10 * - the Linux "gadget" slave/device/peripheral side driver API.
24 * [b] so that accessing bigger-than-a-bytes fields will never
29 * someone that the two other points are non-issues for that
40 /*-------------------------------------------------------------------------*/
132 * See USB 2.0 spec Table 9-7
142 * See USB 3.0 spec Table 9-6
151 * Suspend Options, Table 9-7 USB 3.0 spec
164 * struct usb_ctrlrequest - SETUP data for a USB device control request
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/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
26 typedef unsigned int Word32 ;
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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