| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
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| /openbmc/linux/include/linux/mux/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
22 * struct mux_control_ops - Mux controller operations for a mux chip.
30 * struct mux_control - Represents a mux controller.
33 * @cached_state: The current mux controller state, or -1 if none.
57 * struct mux_chip - Represents a chip holding mux controllers.
58 * @controllers: Number of mux controllers handled by the chip.
59 * @mux: Array of mux controllers that are handled.
65 unsigned int controllers; member
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | renesas,dbsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas DDR Bus Controllers
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 Renesas SoCs contain one or more memory controllers. These memory
14 controllers differ from one SoC variant to another, and are called by
21 - renesas,dbsc-r8a73a4 # R-Mobile APE6
22 - renesas,dbsc3-r8a7740 # R-Mobile A1
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| H A D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
20 - Marek Vasut <marex@denx.de>
26 bank-width:
32 - reg
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| /openbmc/linux/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
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| H A D | skx_common.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define SKX_NUM_IMC 2 /* Memory controllers per socket */
33 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
61 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
62 * memory errors should fit one of these masks:
73 * Errors from either the memory of the 1-level memory system or the
74 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
78 * Errors from the 1st level memory (the fast "near" memory as cache)
79 * of the 2-level memory system.
86 * memory controllers on the die.
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
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| /openbmc/linux/Documentation/devicetree/bindings/mips/brcm/ |
| H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /openbmc/u-boot/board/freescale/ls1012ardb/ |
| H A D | README | 2 --------
3 QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
73 and Toshiba(R). Most controllers found in laptops are of this type.
85 need to overwrite SDHCI IO memory accessors.
94 implements a hardware byte swapper using a 32-bit datum.
109 Most controllers found today are PCI devices.
123 disabled, it will steal the MMC cards away - rendering them
130 tristate "SDHCI support for ACPI enumerated SDHCI controllers"
134 This selects support for ACPI enumerated SDHCI controllers,
154 tristate "SDHCI OF support for the Arasan SDHCI controllers"
218 tristate "SDHCI OF support for the Nintendo Wii SDHCI controllers"
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| /openbmc/linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 10 can do Atomic Transactions to the memory internally.
12 2. With and without An Intelligent Memory Controller which
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
30 Virtually all customers buy their memory controllers from vendors that
31 don't support atomic RCW memory transactions and will likely want to
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| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
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| /openbmc/linux/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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| /openbmc/qemu/docs/system/devices/ |
| H A D | nvme.rst | 5 QEMU provides NVMe emulation through the ``nvme``, ``nvme-ns`` and
6 ``nvme-subsys`` devices.
11 * Configuration of `Optional Features`_ such as `Controller Memory Buffer`_,
12 `Simple Copy`_, `Zoned Namespaces`_, `metadata`_ and `End-to-End Data
19 --------------------
32 .. code-block:: console
34 -drive file=nvm.img,if=none,id=nvm
35 -device nvme,serial=deadbeef,drive=nvm
38 are mentioned here, but see ``-device nvme,help`` to list all possible
46 The number of MSI-X vectors that the device should support.
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| /openbmc/linux/drivers/spi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
24 work with most such devices and controllers.
44 If your system has an master-capable SPI controller (which
52 bool "SPI memory extension"
54 Enable this option if you want to enable the SPI memory extension.
56 by providing a high-level interface to send memory-like commands.
112 tristate "Aspeed flash controllers in SPI mode"
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| /openbmc/linux/drivers/scsi/aic7xxx/ |
| H A D | aic7xxx_osm_pci.c | 2 * Linux driver attachment glue for PCI based controllers.
4 * Copyright (c) 2000-2001 Adaptec Inc.
18 * 3. Neither the names of the above-listed copyright holders nor the names
50 /* aic7850 based controllers */
52 /* aic7860 based controllers */
58 /* aic7870 based controllers */
65 /* aic7880 based controllers */
75 /* aic7890 based controllers */
83 /* aic7890 based controllers */
91 /* aic7892 based controllers */
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| /openbmc/u-boot/drivers/core/ |
| H A D | Kconfig | 7 support, including scanning of platform data on start-up. If
45 This will cause dm_warn() to be compiled out - it will do nothing
63 it causes unplugged devices to linger around in the dm-tree, and it
64 causes USB host controllers to not be stopped when booting the OS.
110 direct memory access.
120 direct memory access.
130 direct memory access.
133 bool "Support system controllers"
136 Many SoCs have a number of system controllers which are dealt with
142 bool "Support system controllers in SPL"
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /openbmc/u-boot/doc/ |
| H A D | README.uefi | 1 <!--
2 SPDX-License-Identifier: GPL-2.0+
5 -->
7 # UEFI on U-Boot
17 The implementation of UEFI in U-Boot strives to reach the minimum requirements
18 described in "Server Base Boot Requirements System Software on ARM Platforms -
21 A full blown UEFI implementation would contradict the U-Boot design principle
26 The UEFI standard supports only little-endian systems. The UEFI support can be
47 * image address - the memory address of the UEFI binary
48 * fdt address - the memory address of the flattened device tree
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| /openbmc/linux/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
17 the physical memory read back to the requester.
19 With that, it is possible to debug issues by reading interesting memory
22 Retrieving a full system memory dump is also possible over the FireWire,
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