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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
22 - arm,pl080
23 - arm,pl081
25 - compatible
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H A Dlpc1850-dmamux.txt4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
15 - dma-requests: Number of DMA requests the controller can handle
20 compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
21 arm,primecell-periphid = <0x00041080>;
25 clock-names = "apb_pclk";
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/openbmc/u-boot/drivers/misc/
H A Dcros_ec.c1 // SPDX-License-Identifier: GPL-2.0+
28 #include <asm-generic/gpio.h>
29 #include <dm/device-internal.h>
31 #include <dm/uclass-internal.h>
100 if (cmd != -1) in cros_ec_dump_data()
109 * Calculate a simple 8-bit checksum of a data block
112 * @param size Size of data block in bytes
115 int cros_ec_calc_checksum(const uint8_t *data, int size) in cros_ec_calc_checksum() argument
119 for (i = csum = 0; i < size; i++) in cros_ec_calc_checksum()
129 * @param dev CROS-EC device
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/openbmc/linux/include/linux/amba/
H A Dpl08x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
6 * Copyright (C) 2010 ST-Ericsson SA
32 * struct pl08x_channel_data - data structure to pass info between
48 * can be the address of a FIFO register for burst requests for example.
84 * struct pl08x_platform_data - the platform configuration for the PL08x
91 * @memcpy_burst_size: the appropriate burst size for memcpy operations
93 * @memcpy_prot_buff: whether memcpy DMA is bufferable
94 * @memcpy_prot_cache: whether memcpy DMA is cacheable
/openbmc/linux/drivers/dma/
H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
36 * On burst request from peripheral
37 * Destination burst from DMAC to peripheral
38 * Clear burst request
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H A Dnbpfaxi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
10 #include <linux/dma-mapping.h>
22 #include <dt-bindings/dma/nbpfaxi.h>
61 #define NBPF_CHAN_CFG_SDS 0xf000 /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
62 #define NBPF_CHAN_CFG_DDS 0xf0000 /* Destination Data Size: as above */
104 * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
108 * allocated from coherent memory - one per SG segment
115 * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
142 * struct nbpf_desc - DMA transfer descriptor
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H A Dste_dma40.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Maxium size for a single dma descriptor
8 * Size is limited to 16 bits.
9 * Size is in the units of addr-widths (1,2,4,8 bytes)
14 /* dev types for memcpy */
15 #define STEDMA40_DEV_DST_MEMORY (-1)
16 #define STEDMA40_DEV_SRC_MEMORY (-1)
38 /* The value 4 indicates that PEN-reg shall be set to 0 */
63 * struct stedma40_half_channel_info - dst/src channel configuration
67 * @p_size: Burst size
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H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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/openbmc/linux/net/netfilter/
H A Dxt_hashlimit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * xt_hashlimit - Netfilter module to limit the number of packets per time
6 * (C) 2003-2004 by Harald Welte <laforge@netfilter.org>
7 * (C) 2006-2012 Patrick McHardy <kaber@trash.net>
8 * Copyright © CC Computer Consultants GmbH, 2007 - 2008
50 MODULE_DESCRIPTION("Xtables: per hash-bucket rate-limit match");
90 /* static / read-only parts in the beginning */
109 int64_t burst; member
144 to->mode = cfg->mode; in cfg_copy()
145 to->avg = cfg->avg; in cfg_copy()
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dcn10k.c1 // SPDX-License-Identifier: GPL-2.0
33 if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) { in cn10k_lmtst_init()
34 pfvf->hw_ops = &otx2_hw_ops; in cn10k_lmtst_init()
38 pfvf->hw_ops = &cn10k_hw_ops; in cn10k_lmtst_init()
39 /* Total LMTLINES = num_online_cpus() * 32 (For Burst flush).*/ in cn10k_lmtst_init()
40 pfvf->tot_lmt_lines = (num_online_cpus() * LMT_BURST_SIZE); in cn10k_lmtst_init()
41 pfvf->hw.lmt_info = alloc_percpu(struct otx2_lmt_info); in cn10k_lmtst_init()
43 mutex_lock(&pfvf->mbox.lock); in cn10k_lmtst_init()
44 req = otx2_mbox_alloc_msg_lmtst_tbl_setup(&pfvf->mbox); in cn10k_lmtst_init()
46 mutex_unlock(&pfvf->mbox.lock); in cn10k_lmtst_init()
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H A Dotx2_tc.c1 // SPDX-License-Identifier: GPL-2.0
49 u32 burst; member
53 static void otx2_get_egress_burst_cfg(struct otx2_nic *nic, u32 burst, in otx2_get_egress_burst_cfg() argument
59 if (is_dev_otx2(nic->pdev)) { in otx2_get_egress_burst_cfg()
67 /* Burst is calculated as in otx2_get_egress_burst_cfg()
69 * Max supported burst size is 130,816 bytes. in otx2_get_egress_burst_cfg()
71 burst = min_t(u32, burst, max_burst); in otx2_get_egress_burst_cfg()
72 if (burst) { in otx2_get_egress_burst_cfg()
73 *burst_exp = ilog2(burst) ? ilog2(burst) - 1 : 0; in otx2_get_egress_burst_cfg()
74 tmp = burst - rounddown_pow_of_two(burst); in otx2_get_egress_burst_cfg()
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/openbmc/u-boot/drivers/tpm/
H A Dtpm_tis_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <tpm-v1.h>
87 /* Retrieve burst count value out of the status register contents. */
99 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_byte()
107 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_word()
114 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_byte()
122 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_word()
132 * @reg - pointer to the TPM register
133 * @mask - bitmask for the bitfield(s) to watch
134 * @expected - value the field(s) are supposed to be set to
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/openbmc/linux/Documentation/driver-api/dmaengine/
H A Dprovider.rst20 DMA-eligible devices to the controller itself. Whenever the device
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
42 using a parameter called the burst size, that defines how many single
44 transfer into smaller sub-transfers.
49 non-contiguous buffers to a contiguous buffer, which is called
50 scatter-gather.
53 scatter-gather. So we're left with two cases here: either we have a
56 that implements in hardware scatter-gather.
72 not and the three parameters we saw earlier: the burst size, the
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/openbmc/linux/drivers/dma/qcom/
H A Dqcom_adm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
29 /* ADM registers - calculated from channel number and security domain */
99 #define ADM_MAX_XFER (SZ_64K - 1)
100 #define ADM_MAX_ROWS (SZ_64K - 1)
177 * adm_free_chan - Frees dma resources associated with the specific channel
190 * adm_get_blksize - Get block size from burst value
192 * @burst: Burst size of transaction
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/openbmc/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_acl.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2020-2021 Marvell International Ltd. All rights reserved. */
22 #define rule_match_set_n(match_p, type, val_p, size) \ argument
23 memcpy(&(match_p)[PRESTERA_ACL_RULE_MATCH_TYPE_##type], \
24 val_p, size)
26 memcpy(&(match_p)[PRESTERA_ACL_RULE_MATCH_TYPE_##type], \
117 u64 burst; member
/openbmc/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
28 #include "../virt-dma.h"
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
101 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
102 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
103 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
104 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 * fail. Today davinci-pcm is the only user of this driver and
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/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2010 Nokia Corporation
44 strncpy(wl->chip.fw_ver_str, static_data->fw_version, in wlcore_boot_parse_fw_ver()
45 sizeof(wl->chip.fw_ver_str)); in wlcore_boot_parse_fw_ver()
47 /* make sure the string is NULL-terminated */ in wlcore_boot_parse_fw_ver()
48 wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0'; in wlcore_boot_parse_fw_ver()
50 ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u", in wlcore_boot_parse_fw_ver()
51 &wl->chip.fw_ver[0], &wl->chip.fw_ver[1], in wlcore_boot_parse_fw_ver()
52 &wl->chip.fw_ver[2], &wl->chip.fw_ver[3], in wlcore_boot_parse_fw_ver()
53 &wl->chip.fw_ver[4]); in wlcore_boot_parse_fw_ver()
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/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <media/rc-core.h>
34 #include "sil-sii8620.h"
101 } burst; member
128 0x61, /* eCBUS-S, eCBUS-D */
139 int ret = ctx->error; in sii8620_clear_error()
141 ctx->error = 0; in sii8620_clear_error()
147 struct device *dev = ctx->dev; in sii8620_read_buf()
153 .flags = client->flags, in sii8620_read_buf()
159 .flags = client->flags | I2C_M_RD, in sii8620_read_buf()
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/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_sup.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
18 * qla2x00_lock_nvram_access() -
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_lock_nvram_access()
28 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
31 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
35 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
36 rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
38 data = rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
42 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
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/openbmc/linux/drivers/media/dvb-frontends/
H A Dcx24116.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
5 Copyright (C) 2006-2008 Steven Toth <stoth@hauppauge.com>
6 Copyright (C) 2006-2007 Georg Acher
7 Copyright (C) 2007-2008 Darron Broad
45 #define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
74 /* Select DVB-S demodulator, else DVB-S2 */
81 /* arg buffer size */
115 /* DiSEqC burst */
119 /* DiSEqC tone burst */
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/openbmc/u-boot/drivers/video/
H A Dipu_common.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Porting to u-boot:
10 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
19 #include <asm/arch/imx-regs.h>
41 (((struct ipu_ch_param *)(base))->word[(w)].data)
43 #define ipu_ch_param_set_field(base, w, bit, size, v) { \ argument
47 if (((bit) + (size) - 1) / 32 > i) { \
48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
52 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \ argument
55 u32 mask = (1UL << size) - 1; \
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/openbmc/linux/drivers/bus/
H A Dimx-weim.c16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
75 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
77 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
79 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
80 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
82 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
89 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
104 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); in imx_weim_gpr_setup()
106 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); in imx_weim_gpr_setup()
115 val = (range.size / SZ_32M) | 1; in imx_weim_gpr_setup()
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/openbmc/linux/drivers/net/ethernet/qualcomm/
H A Dqca_debug.c75 struct qcaspi *qca = s->private; in qcaspi_info_show()
77 seq_printf(s, "RX buffer size : %lu\n", in qcaspi_info_show()
78 (unsigned long)qca->buffer_size); in qcaspi_info_show()
82 if (qca->txr.skb[qca->txr.head] == NULL) in qcaspi_info_show()
84 else if (qca->txr.skb[qca->txr.tail]) in qcaspi_info_show()
91 seq_printf(s, "TX ring size : %u\n", in qcaspi_info_show()
92 qca->txr.size); in qcaspi_info_show()
95 (unsigned int)qca->sync); in qcaspi_info_show()
96 switch (qca->sync) { in qcaspi_info_show()
113 qca->spi_dev->irq); in qcaspi_info_show()
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/openbmc/linux/drivers/infiniband/sw/siw/
H A Dsiw_qp_tx.c1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
4 /* Copyright (c) 2008-2019, IBM Corporation */
22 (((uint32_t)(sizeof(struct siw_rreq_pkt) - \
27 struct siw_pbl *pbl = mem->pbl; in siw_get_pblpage()
28 u64 offset = addr - mem->va; in siw_get_pblpage()
42 struct siw_wqe *wqe = &c_tx->wqe_active; in siw_try_1seg()
43 struct siw_sge *sge = &wqe->sqe.sge[0]; in siw_try_1seg()
44 u32 bytes = sge->length; in siw_try_1seg()
46 if (bytes > MAX_HDR_INLINE || wqe->sqe.num_sge != 1) in siw_try_1seg()
53 memcpy(paddr, &wqe->sqe.sge[1], bytes); in siw_try_1seg()
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