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/openbmc/linux/drivers/memory/
H A Dpl353-smc.c20 * @memclk: Pointer to the peripheral clock
24 struct clk *memclk; member
32 clk_disable(pl353_smc->memclk); in pl353_smc_suspend()
49 ret = clk_enable(pl353_smc->memclk); in pl353_smc_resume()
90 pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk"); in pl353_smc_probe()
91 if (IS_ERR(pl353_smc->memclk)) { in pl353_smc_probe()
92 dev_err(&adev->dev, "memclk clock not found.\n"); in pl353_smc_probe()
93 return PTR_ERR(pl353_smc->memclk); in pl353_smc_probe()
102 err = clk_prepare_enable(pl353_smc->memclk); in pl353_smc_probe()
131 clk_disable_unprepare(pl353_smc->memclk); in pl353_smc_probe()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h280 * Send message to PMFW to set hard min memclk frequency
286 /* Send message to PMFW to set hard max memclk frequency to highest DPM */
289 /* Custom set a memclk freq range*/
293 /* Get current memclk states from PMFW, update relevant structures */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml134 - const: memclk
142 clock-names = "memclk", "apb_pclk";
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c588 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
593 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
629 { .fclk = 400, .memclk = 400, .voltage = 2800 },
630 { .fclk = 400, .memclk = 400, .voltage = 2800 },
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 }
H A Ddcn301_smu.h33 uint32_t memclk; member
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml38 clock-names = "memclk", "apb_pclk";
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c354 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
375 /* Set max memclk to highest DPM value */
405 /* Get current memclk states, update bounding box */
414 /* Refresh memclk states */ in dcn3_get_memclk_states_from_smu()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c512 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
524 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
708 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn315_clk_mgr_construct()
711 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn315_clk_mgr_construct()
H A Ddcn315_smu.h63 uint32_t MemClk; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h41 uint32_t MemClk; member
H A Ddcn314_clk_mgr.c623 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
639 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
823 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn314_clk_mgr_construct()
826 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn314_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c805 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
826 /* Set max memclk to highest DPM value */
837 /* Get current memclk states, update bounding box */
847 /* Refresh memclk and fclk states */ in dcn32_get_memclk_states_from_smu()
854 /* memclk must have at least one level */ in dcn32_get_memclk_states_from_smu()
/openbmc/openbmc/meta-hpe/meta-dl360poc/recipes-kernel/linux/linux-obmc/
H A Dgxp.dts701 memclk: memclk { label
705 clock-out-put-names = "memclk";
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h69 uint32_t MemClk; member
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h79 uint32_t MemClk; member
H A Dsmu13_driver_if_yellow_carp.h113 uint32_t MemClk; member
H A Dsmu11_driver_if_vangogh.h115 uint32_t memclk; member
H A Dsmu13_driver_if_v13_0_4.h114 uint32_t MemClk; member
/openbmc/linux/arch/arm/include/uapi/asm/
H A Dsetup.h168 struct tag_memclk memclk; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
781 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" in dcn31_clk_mgr_construct()
784 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, in dcn31_clk_mgr_construct()
H A Ddcn31_smu.h122 uint32_t MemClk; member
/openbmc/linux/arch/arm/mach-footbridge/
H A Dcommon.c130 mem_fclk_21285 = tag->u.memclk.fmemclk; in parse_tag_memclk()
/openbmc/u-boot/arch/arm/include/asm/
H A Dsetup.h229 struct tag_memclk memclk; member
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.c625 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", in vega20_setup_memclk_dpm_table()
672 /* memclk */ in vega20_setup_default_dpm_tables()
1556 "[SetMclkOD] failed to set od memclk!", in vega20_set_mclk_od()
1559 /* retrieve updated memclk table */ in vega20_set_mclk_od()
1562 "[SetMclkOD] failed to refresh memclk table!", in vega20_set_mclk_od()
1845 "Failed to set soft min memclk !", in vega20_upload_dpm_min_level()
1948 "Failed to set soft max memclk!", in vega20_upload_dpm_max_level()
2097 "[MemMclks]: memclk dpm not enabled!\n", in vega20_dpm_get_mclk()
3163 /* retrieve updated memclk table */ in vega20_odn_edit_dpm_table()
3777 /* memclk */ in vega20_apply_clocks_adjust_rules()
[all …]
/openbmc/linux/arch/arm/kernel/
H A Datags_compat.c165 tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285; in build_tag_list()

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