| /openbmc/linux/drivers/mailbox/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig MAILBOX config
3 bool "Mailbox Hardware Support"
5 Mailbox is a framework to control hardware communication between
6 on-chip processors through queued messages and interrupt driven
9 if MAILBOX
12 tristate "Apple Mailbox driver"
16 Apple SoCs have various co-processors required for certain
18 driver adds support for the mailbox controller used to
24 tristate "ARM MHU Mailbox"
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 # Generic MAILBOX API
4 obj-$(CONFIG_MAILBOX) += mailbox.o
6 obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o
8 obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o
10 obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o
12 obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
14 obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
16 obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o
18 obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
35 lines can also be routed to different processor sub-systems on DRA7xx as they
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| H A D | hisilicon,hi6220-mailbox.txt | 1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
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| H A D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
15 #mbox-cells = <1>;
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
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| H A D | apple,mailbox.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Mailbox Controller
10 - Hector Martin <marcan@marcan.st>
11 - Sven Peter <sven@svenpeter.dev>
14 The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
15 messages between the main CPU and a co-processor. Multiple instances
16 of this mailbox can be found on Apple SoCs.
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| H A D | altera-mailbox.txt | 1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
12 - interrupts : interrupt number. The interrupt specifier format
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
19 interrupt-parent = < &gic_0 >;
21 #mbox-cells = <1>;
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| H A D | microchip,mpfs-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
10 - Conor Dooley <conor.dooley@microchip.com>
14 const: microchip,mpfs-mailbox
18 - items:
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
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| H A D | xgene-slimpro-mailbox.txt | 1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
22 Mailbox Node:
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| /openbmc/u-boot/include/ |
| H A D | mailbox.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * A mailbox is a hardware mechanism for transferring small fixed-size messages
11 * and/or notifications between the CPU on which U-Boot runs and some other
14 * Data transfer is optional; a mailbox may consist solely of a notification
16 * FIFOs, rather than via RAM-based buffers. The mailbox API generally
18 * leaves any higher-level protocols to other layers.
20 * A mailbox channel is a bi-directional mechanism that can send a message or
23 * messages is defined by the mailbox implementation, or the remote entity with
26 * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
27 * will often implement multiple separate mailbox channels, since the hardware
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | fw_qos.c | 16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
58 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
87 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_PRIO2TC() local
93 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_PRIO2TC()
94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
100 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; in mlx4_SET_PORT_PRIO2TC()
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, in mlx4_SET_PORT_PRIO2TC()
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| H A D | srq.c | 15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
45 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; in mlx4_srq_event()
49 srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1)); in mlx4_srq_event()
52 refcount_inc(&srq->refcount); in mlx4_srq_event()
58 srq->event(srq, event_type); in mlx4_srq_event()
60 if (refcount_dec_and_test(&srq->refcount)) in mlx4_srq_event()
61 complete(&srq->free); in mlx4_srq_event()
64 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_SRQ() argument
67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, in mlx4_SW2HW_SRQ()
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| /openbmc/linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_vf_mbx.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * @v_opcode: opcodes for VF-PF communication
17 * Send message to VF driver (0x0802) using mailbox
31 cmd->id = cpu_to_le32(vfid); in ice_aq_send_msg_to_vf()
39 return ice_sq_send_cmd(hw, &hw->mailboxq, &desc, msg, msglen, cd); in ice_aq_send_msg_to_vf()
71 u32 index = fls(link_speed) - 1; in ice_conv_link_speed_to_virtchnl()
86 /* The mailbox overflow detection algorithm helps to check if there
89 * 1. The mailbox snapshot structure, ice_mbx_snapshot, is initialized during
92 * messages within the mailbox queue while looking for a malicious VF.
94 * 2. When the caller starts processing its mailbox queue in response to an
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| /openbmc/u-boot/doc/device-tree-bindings/mailbox/ |
| H A D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
15 #mbox-cells = <1>;
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | acpi_parking_protocol.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 struct parking_protocol_mailbox __iomem *mailbox; member
34 cpu_entry->mailbox_addr = p->parked_address; in acpi_set_mailbox_entry()
35 cpu_entry->version = p->parking_version; in acpi_set_mailbox_entry()
36 cpu_entry->gic_cpu_id = p->cpu_interface_number; in acpi_set_mailbox_entry()
43 return cpu_entry->mailbox_addr && cpu_entry->version; in acpi_parking_protocol_valid()
62 struct parking_protocol_mailbox __iomem *mailbox; in acpi_parking_protocol_cpu_boot() local
66 * Map mailbox memory with attribute device nGnRE (ie ioremap - in acpi_parking_protocol_cpu_boot()
71 * If the mailbox is mistakenly allocated in the linear mapping in acpi_parking_protocol_cpu_boot()
76 mailbox = ioremap(cpu_entry->mailbox_addr, sizeof(*mailbox)); in acpi_parking_protocol_cpu_boot()
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| /openbmc/linux/drivers/scsi/lpfc/ |
| H A D | lpfc_mbox.c | 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
47 * lpfc_mbox_rsrc_prep - Prepare a mailbox with DMA buffer memory.
49 * @mbox: pointer to the driver internal queue element for mailbox command.
51 * A mailbox command consists of the pool memory for the command, @mbox, and
69 return -ENOMEM; in lpfc_mbox_rsrc_prep()
71 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys); in lpfc_mbox_rsrc_prep()
72 if (!mp->virt) { in lpfc_mbox_rsrc_prep()
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| /openbmc/linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_cmd.c | 16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
151 * commands. So we can't use strict timeouts described in PRM -- we
194 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit()
206 void __iomem *ptr = dev->cmd.dbell_map; in mthca_cmd_post_dbell()
207 u16 *offs = dev->cmd.dbell_offsets; in mthca_cmd_post_dbell()
249 return -EAGAIN; in mthca_cmd_post_hcr()
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr()
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); in mthca_cmd_post_hcr()
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| H A D | mthca_mcg.c | 14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
54 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
60 * If no AMGM exists for given gid, *index = -1, *prev = index of last
67 struct mthca_mailbox *mailbox; in find_mgm() local
68 struct mthca_mgm *mgm = mgm_mailbox->buf; in find_mgm()
72 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in find_mgm()
73 if (IS_ERR(mailbox)) in find_mgm()
74 return -ENOMEM; in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
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| /openbmc/openbmc/meta-yadro/recipes-phosphor/dbus/phosphor-dbus-interfaces/ |
| H A D | 0001-Add-boot-initiator-mailbox-interface.patch | 4 Subject: [PATCH] Add boot initiator mailbox interface
6 Add the xyz.openbmc_project.Control.Boot.Mailbox interface to allow
8 its specific parameters. This is based on IPMI 2.0 Table 28-14 'Boot
9 Option Parameters' parameter 7 'Boot initiator mailbox'.
13 Change-Id: If2a7dce6fae812fc3f1f325cd07c77f31900cf42
14 Signed-off-by: Alexander Amelkin <a.amelkin@yadro.com>
15 ---
16 .../Control/Boot/Mailbox/meson.build | 14 +++++
18 .../Control/Boot/Mailbox.interface.yaml | 63 +++++++++++++++++++
20 create mode 100644 gen/xyz/openbmc_project/Control/Boot/Mailbox/meson.build
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| /openbmc/linux/drivers/net/ethernet/intel/fm10k/ |
| H A D | fm10k_mbx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
17 fifo->tail = 0; in fm10k_fifo_init()
21 * fm10k_fifo_used - Retrieve used space in FIFO
28 return fifo->tail - fifo->head; in fm10k_fifo_used()
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| H A D | fm10k_mbx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
13 /* PF Mailbox Registers */
32 /* VF Mailbox Registers */
43 /* PF/VF Mailbox state machine
45 * +----------+ connect() +----------+
46 * | CLOSED | --------------> | CONNECT |
47 * +----------+ +----------+
54 * +----------+ disconnect() +----------+
55 * |DISCONNECT| <-------------- | OPEN |
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| /openbmc/linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_mbx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 * igb_read_mbx - Reads a message from the mailbox
11 * @mbx_id: id of mailbox to read
19 struct e1000_mbx_info *mbx = &hw->mbx; in igb_read_mbx()
20 s32 ret_val = -E1000_ERR_MBX; in igb_read_mbx()
22 /* limit read to size of mailbox */ in igb_read_mbx()
23 if (size > mbx->size) in igb_read_mbx()
24 size = mbx->size; in igb_read_mbx()
26 if (mbx->ops.read) in igb_read_mbx()
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/uw-imap/uw-imap/ |
| H A D | uw-imap-fix-incompatible-pointer-types.patch | 1 Fix compile errors when gcc option '-Wincompatible-pointer-types' set:
4 … error: passing argument 2 of 'utime' from incompatible pointer type [-Wincompatible-pointer-types]
10 Upstream-Status: Inactive-Upstream [lastrelease: 2011]
14 Signed-off-by: Kai Kang <kai.kang@windriver.com>
16 ---
17 src/osdep/unix/mbx.c | 12 ++++++------
18 src/osdep/unix/mh.c | 2 +-
19 src/osdep/unix/mmdf.c | 10 +++++-----
20 src/osdep/unix/mtx.c | 16 ++++++++--------
21 src/osdep/unix/mx.c | 2 +-
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| /openbmc/linux/drivers/scsi/csiostor/ |
| H A D | csio_mb.c | 4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
51 * csio_mb_fw_retval - FW return value from a mailbox response.
52 * @mbp: Mailbox structure
60 hdr = (struct fw_cmd_hdr *)(mbp->mb); in csio_mb_fw_retval()
62 return FW_CMD_RETVAL_G(ntohl(hdr->lo)); in csio_mb_fw_retval()
66 * csio_mb_hello - FW HELLO command helper
68 * @mbp: Mailbox structure
69 * @m_mbox: Master mailbox number, if any.
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| /openbmc/linux/drivers/infiniband/hw/hns/ |
| H A D | hns_roce_cmd.c | 14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
44 return hr_dev->hw->post_mbox(hr_dev, mbox_msg); in hns_roce_cmd_mbox_post_hw()
55 dev_err_ratelimited(hr_dev->dev, in __hns_roce_cmd_mbox_poll()
56 "failed to post mailbox 0x%x in poll mode, ret = %d.\n", in __hns_roce_cmd_mbox_poll()
57 mbox_msg->cmd, ret); in __hns_roce_cmd_mbox_poll()
61 return hr_dev->hw->poll_mbox_done(hr_dev); in __hns_roce_cmd_mbox_poll()
69 down(&hr_dev->cmd.poll_sem); in hns_roce_cmd_mbox_poll()
71 up(&hr_dev->cmd.poll_sem); in hns_roce_cmd_mbox_poll()
80 &hr_dev->cmd.context[token % hr_dev->cmd.max_cmds]; in hns_roce_cmd_event()
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